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| W83697SF WINBOND I/O W83697SF Data Sheet Revision History Pages Dates Version Version on Web 1 2 3 4 5 6 7 8 9 10 n.a. 111 04/16/01 04/27/01 0.50 0.51 0.50 0.51 First published Update the Top Marking Main Contents Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. W83697SF PRELIMINARY TABLE OF CONTENT GENERAL DESCRIPTION.............................................................................................................. 1 PIN CONFIGURATION FO R 697SF ................................................................................................ 6 1.0 PIN DESCRIPTION ................................................................................................................ 7 1.1 LPC INTERFACE........................................................................................................................ 7 1.2 FDC INTERFACE........................................................................................................................ 9 1.3 MULTI-MODE PARALLEL PORT.....................................................................................................10 1.4 SERIAL PORT INTERFACE............................................................................................................15 1.5 INFRARED PORT........................................................................................................................16 1.6 FRESH ROM INTERFACE.............................................................................................................16 1.7 GENERAL PURPOSE I/O PORT .....................................................................................................17 1.8 SMART CARD INTERFACE............................................................................................................17 1.9 PWM & GENERAL PURPOSE I/O PORT 8 ......................................................................................18 1.10 GAME PORT & MIDI PORT........................................................................................................18 1.11 POWER PINS ......................................................................................................................19 2.0 LPC (LOW PIN COUNT) INTERFACE......................................................................................20 3.0 FDC FUNCTIONAL DESCRIPTION .........................................................................................21 3.1 W83697SF FDC.....................................................................................................................21 3.1.1 AT interface.....................................................................................................................21 3.1.2 FIFO (Data) .....................................................................................................................21 3.1.3 Data Separator.................................................................................................................22 3.1.4 Write Precompensation.....................................................................................................22 3.1.5 Perpendicular Recording Mode...........................................................................................23 3.1.6 FDC Core ........................................................................................................................23 3.1.7 FDC Commands...............................................................................................................23 3.2 REGISTER DESCRIPTIONS.............................................................................................................36 3.2.1 Status Register A (SA Register) (Read base address + 0) ...................................................36 3.2.2 Status Register B (SB Register) (Read base address + 1) ...................................................38 3.2.3 Digital Output Register (DO Register) (Write base address + 2)............................................40 3.2.4. Tape Drive Register (TD Register) (Read base address + 3)................................................40 3.2.5 Main Status Register (MS Register) (Read base address + 4)...............................................43 3.2.6 Data Rate Register (DR Register) (Write base address + 4) .................................................43 3.2.7 FIFO Register (R/W base address + 5) ..............................................................................45 3.2.8 Digital Input Register (DI Register) (Read base address + 7) ................................................46 3.2.9 Configuration Control Register (CC Register) (Write base address + 7)..................................48 4.0 UART PORT..........................................................................................................................49 -I- Publication Release Date: April 2001 Revision 0.50 W83697SF PRELIMINARY 4.1 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART A, UART B)..........................................49 4.2 REGISTER ADDRESS...................................................................................................................49 4.2.1 UART Control Register (UCR) (Read/Write).........................................................................49 4.2.2 UART Status Register (USR) (Read/Write) .........................................................................51 4.2.3 Handshake Control Register (HCR) (Read/Write).................................................................52 4.2.4 Handshake Status Register (HSR) (Read/Write)..................................................................53 4.2.5 UART FIFO Control Register (SFR) (Write only) ..................................................................54 4.2.6 Interrupt Status Register (ISR) (Read only) .........................................................................55 4.2.7 Interrupt Control Register (ICR) (Read/Write).......................................................................57 4.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write) ......................................................57 4.2.9 User-defined Register (UDR) (Read/Write) ..........................................................................58 5.0 PARALLEL PORT.................................................................................................................59 5.1 PRINTER INTERFACE LOGIC ..........................................................................................................59 5.2 ENHANCED PARALLEL PORT (EPP)..............................................................................................60 5.2.1 Data Swapper...................................................................................................................62 5.2.2 Printer Status BSFfer .......................................................................................................62 5.2.3 Printer Control Latch and Printer Control Swapper................................................................62 5.2.4 EPP Address Port ............................................................................................................63 5.2.5 EPP Data Port 0-3............................................................................................................64 5.2.6 Bit Map of Parallel Port and EPP Registers ........................................................................64 5.2.7 EPP Pin Descriptions .......................................................................................................66 5.2.8 EPP Operation .................................................................................................................66 5.3 EXTENDED CAPABILITIES PARALLEL (ECP) PORT............................................................................68 5.3.1 ECP Register and Mode Definitions....................................................................................68 5.3.2 Data and ecpAFifo Port.....................................................................................................69 5.3.3 Device Status Register (DSR)............................................................................................69 5.3.4 Device Control Register (DCR)...........................................................................................70 5.3.5 cFifo (Parallel Port Data FIFO) Mode = 010 ........................................................................71 5.3.6 ecpDFifo (ECP Data FIFO) Mode = 011..............................................................................71 5.3.7 tFifo (Test FIFO Mode) Mode = 110 ...................................................................................71 5.3.8 cnfgA (Configuration Register A) Mode = 111......................................................................71 5.3.9 cnfgB (Configuration Register B) Mode = 111......................................................................71 5.3.10 ecr (Extended Control Register) Mode = all........................................................................72 5.3.11 Bit Map of ECP Port Registers.........................................................................................73 5.3.12 ECP Pin Descriptions .....................................................................................................75 5.3.13 ECP Operation ...............................................................................................................76 5.3.14 FIFO Operation ..............................................................................................................76 5.3.15 DMA Transfers ...............................................................................................................77 5.3.16 Programmed I/O (NON-DMA) Mode ..................................................................................77 5.4 EXTENSION FDD MODE (EXTFDD)...............................................................................................77 5.5 EXTENSION 2FDD MODE (EXT2FDD) ...........................................................................................77 6.0 GENERAL PURPOSE I/O.......................................................................................................78 7.0 ACPI REGISTERS FEATURES ...............................................................................................82 - II - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 8.0 PULSE WIDTH MODULATION (PWM) ....................................................................................83 8.1 GENERAL DESCRIPTION...............................................................................................................83 8.2 LPC INTERFACE.......................................................................................................................83 8.3 REGISTERS ..........................................................................................................................84 8.3.1 Address Register (Port x5h)...............................................................................................84 8.3.2 Data Register (Port x6h)....................................................................................................84 8.3.3 PWM 1 Pre-Scale Register -- Index 00h..............................................................................85 8.3.4 PWM 1 Duty Cycle Select Register - Index 01h ..................................................................85 8.3.5 PWM 2 Pre-Scale Register -- Index 02h..............................................................................86 8.3.6 PWM 2 Duty Cycle Select Register -- Index 03h ..................................................................86 8.3.7 PWM 0 Pre-Scale Register -- Index 10h..............................................................................87 8.3.8 PWM 0 Duty Cycle Select Register - Index 11h ..................................................................87 9.0 CONFIGURATION REGISTER ................................................................................................88 9.1 PLUG AND PLAY CONFIGURATION ................................................................................................88 9.2 COMPATIBLE PNP .....................................................................................................................88 9.2.1 Extended Function Registers .............................................................................................88 9.2.2 Extended Functions Enable Registers (EFERs) ..................................................................89 9.2.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs)........89 9.3 CONFIGURATION SEQUENCE.........................................................................................................89 9.3.1 Enter the extended function mode......................................................................................89 9.3.2 Configurate the configuration registers................................................................................89 9.3.3 Exit the extended function mode ........................................................................................89 9.3.4 Software programming example .........................................................................................90 9.4 CHIP (GLOBAL) CONTROL REGISTER .............................................................................................91 9.5 LOGICAL DEVICE 0 (FDC)...........................................................................................................99 9.6 LOGICAL DEVICE 1 (PARALLEL PORT).........................................................................................103 9.7 LOGICAL DEVICE 2 (UART A)....................................................................................................104 9.8 LOGICAL DEVICE 3 (UART B)....................................................................................................105 9.9 LOGICAL DEVICE 7 (GAME PORT AND GPIO PORT 1) .....................................................................107 9.10 LOGICAL DEVICE 8 (MIDI PORT AND GPIO PORT 5).....................................................................108 9.11 LOGICAL DEVICE 9 (GPIO PORT 2 ~ GPIO PORT 4 )...................................................................110 9.12 LOGICAL DEVICE A (ACPI)...................................................................................................... 111 9.13 LOGICAL DEVICE B (PWM) .....................................................................................................117 9.14 LOGICAL DEVICE C (SMART CARD)........................................................................................117 9.15 LOGICAL DEVICE D (URC & GPIO PORT 6 ).............................................................................. 118 9.16 LOGICAL DEVICE E (URD & GPIO PORT 7 ).............................................................................. 119 9.17 LOGICAL DEVICE F (GPIO PORT 8) ..........................................................................................120 10.0 ORDERING INSTRUCTION................................................................................................. 122 11.0 HOW TO READ THE TOP MARKING ..................................................................................122 12.0 PACKAGE DIMENSIONS ....................................................................................................123 - III - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY GENERAL DESCRIPTION The W83697SF is evolving product from Winbond's most popular I/O family. They feature a whole new interface, namely LPC (Low Pin Count) interface, which will be supported in the new generation chipset. This interface as its name suggests is to provide an economical implementation of I/O's interface with lower pin count and still maintains equivalent performance as its ISA interface counterpart. Approximately 40 pin counts are saved in LPC I/O comparing to ISA implementation. With this additional freedom, we can implement more devices on a single chip as demonstrated in W83697SF's integration of Game Port and MIDI Port. It is fully transparent in terms of software which means no BIOS or device driver update is needed except chip-specific configuration. As Smart Card application is gaining more and more attention, W83697SF also implements a smart card reader interface featuring Smart wake-up function. This smart card reader interface fully meets the ISO7816 and PC/SC (Personal Computer/Smart Card Workgroup) standards. W83697SF provides a minimum external components and lowest cost solution for smart card applications. The disk drive adapter functions of W83697SF include a floppy disk drive controller compatible with the industry standard 82077/ 765, data separator, write pre-compensation circuit, decode logic, data rate selection, clock generator, drive interface control logic, and interrupt and DMA logic. The wide range of functions integrated onto the W83697SF greatly reduces the number of components required for interfacing with floppy disk drives. T W83697SF supports four 360K, 720K, 1.2M, 1.44M, or 2.88M he disk drives and data tranSFer rates of 250 Kb/s, 300 Kb/s, 500 Kb/s,1 Mb/s, and 2 Mb/s. The W83697SF provides two high-speed serial communication ports (UARTs), one of which supports serial Infrared communication. Each UART includes a 16-byte send/receive FIFO, a programmable baud rate generator, complete modem control capability, and a processor interrupt system. Both UARTs provide legacy speed with baud rate up to 115.2k bps and also advanced speed with baud rates of 230k, 460k, or 921k bps which support higher speed modems. In addition, the W83697SF provides IR functions: IrDA 1.0 (SIR for 1.152K bps) and TV remote IR ( onsumer IR, supporting NEC, RC-5, C extended RC-5, and RECS-80 protocols). The W83697SF supports one PC-compatible printer port (SPP), Bi-directional Printer port (BPP) and also Enhanced Parallel Port (EPP) and Extended Capabilities Port (ECP). Through the printer port interface pins, also available are: Extension FDD Mode and Ext ension 2FDD Mode allowing one or two external floppy disk drives to be connected. The configuration registers support mode selection, function enable/disable, and power down function selection. Furthermore, the configurable PnP features are compatible with the plug-and-play feature demand of Windows 95/98 TM , which makes system resource allocation more efficient than ever. The W83697SF provides a set of flexible I/O control functions to the system designer through a set of General Purpose I/O ports. These GPIO ports may serve as simple I/O or may be individually configured -1- Publication Release Date: April 2001 Revision 0.50 W83697SF PRELIMINARY to provide a predefined alternate function. General Purpose Port 1 is designed to be functional even in power down mode (VCC is off). The W83697SF is made to fully comply with Microsoft(c) PC98 and PC99 Hardware Design Guide, and meet the requirements of ACPI. The W83697SF contains a game port and a MIDI port. The game port is designed to support 2 joysticks and can be applied to all standard PC game control devices, They are very important for a entertainment or consumer computer. The W83697SF provides Flash ROM interface . That can support up to 4M legacy flash ROM. Moreover, W83697SF support 3 sets PWM Fan Speed Control, which are very important for a highend computer system to work stably and properly. -2- Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY FEATURES General * * * * * * * * Meet LPC Spec. 1.01 Support LDRQ#(LPC DMA), SERIRQ (serial IRQ) Include all the features of Winbond I/O W83877TF Integrate Smart Card functions Compliant with Microsoft PC98/PC99 Hardware Design Guide Support DPM (Device Power Management), ACPI Programmable configuration settings Single 24 or 48 MHz clock input FDC * * * * * * * * * * * * * Compatible with IBM PC AT disk drive systems Variable write pre-compensation with track selectable capability Support vertical recording format DMA enable logic 16-byte data FIFOs Support floppy disk drives and tape drives Detects all overrun and underrun conditions Built-in address mark detection circuit to simplify the read electronics FDD anti-virus functions with software write protect and FDD write enable signal (write data signal was forced to be inactive) Support up to four 3.5-inch or 5.25-inch floppy disk drives Completely compatible with industry standard 82077 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate Support 3-mode FDD, and its Win95/98 driver UART * * * Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs MIDI compatible Fully programmable serial-interface characteristics: --- 5, 6, 7 or 8-bit characters --- Even, odd or no parity bit generation/detection --- 1, 1.5 or 2 stop bits generation Publication Release Date: April 2001 Revision 0.51 -3- W83697SF PRELIMINARY * Internal diagnostic capabilities: --- Loop-back controls for communications link fault isolation --- Break, parity, overrun, framing error simulation * * Programmable baud generator allows division of 1.8461 MHz and 24 MHz by 1 to (216-1) Maximum baud rate up to 921k bps for 14.769 MHz and 1.5M bps for 24 MHz Infrared * * * Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps Support SHARP ASK-IR protocol with maximum baud rate up to 57,600 bps Support Consumer IR with Wake-Up function. Parallel Port * * * * * * Compatible with IBM parallel port Support PS/2 compatible bi-directional parallel port Support Enhanced Parallel Port (EPP) - Compatible with IEEE 1284 specification Support Extended Capabilities Port (ECP) - Compatible with IEEE 1284 specification Extension FDD mode supports disk drive B; and Extension 2FDD mode supports disk drives A and B through parallel port Enhanced printer port back-drive current protection -4- Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY Game Port * * Support two separate Joysticks Support every Joystick two axes (X,Y) and two buttons (S1,S2) controllers MIDI Port * * * The baud rate is 31.25 Kbaud 16-byte input FIFO 16-byte output FIFO Flash ROM Interface * Support up to 4M flash ROM General Purpose I/O Ports * * * 60 programmable general purpose I/O ports General purpose I/O ports can serve as simple I/O ports, watch dog timer output, power LED output, infrared I/O pins, suspend LED output, Beep output Functional in power down mode Smart Card Reader Interface * * ISO7816 protocol compliant PC/SC T=0, T=1 compliant Fan Speed Control * 3 Sets PWM Fan Speed Control Package * 128-pin PQFP -5- Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY PIN CONFIGURATION FOR 697SF GP64 GP65 GP66 GP67 PME# MEMW#/GP52 MEMR#/GP53 ROMCS#/GP54 XD0/GP20 XD1/GP21 XD2/GP22 XD3/GP23 GND XD4/GP24 XD5/GP25 XD6/GP26 XD7/GP27 XA0/GP30 XA1/GP31 XA2/GP32 XA3/GP33 XA4/GP34 XA5/GP35 XA6/GP36 XA7/GP37 XA8/GP40 XA9/GP41 VCC XA10/GP42 XA11/GP43 XA12/GP44 XA13/GP45 XA14/GP46 XA15/GP47 XA16/GP55 XA17/GP56 XA18/GP57 IRTX 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 1 1 1 9 9 9 9 9 9 9 9 9 9 8 8 8 88 8 88 8 8 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 0 0 0 9 8 7 6 5 4 3 21 0 9 8 7 6 5 4 32 1 09 8 7 6 5 4 3 2 1 0 9 8 7 6 5 21 0 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 GP63 GP62 GP61 GP60 SCPSNT/GP77 SCIO/GP76 SCCLK/GP75 SCRST/GP74 GP73 SCC8/GP72 SCPWR/GP71 SCC4/GP70 PWM2/PLED/GP83 PWM1/GP82 PWM0/GP81 WDTO/GP80 MSI/GP51 MSO/GP50 GPAS2/GP17 GPBS2/GP16 GPAY/GP15 GPBY/GP14 GPBX/GP13 GPAX/GP12 GPBS1/GP11 GPAS1/GP10 W83697SF IRRX RIB# DCDB# SOUTB GND SINB DTRB# RTSB# DSRB# CTSB# RIA# DCDA# SOUTA SINA DTRA# RTSA# DSRA# CTSA# STB# VCC AFD# INIT# PD0 PD1 PD2 PD3 1 1 1 1 11 1 1 1 12 2 2 2 22 2 2 2 2 33 3 3 3 3 33 3 1 2 3 4 5 6 7 8 9 0 1 2 3 45 6 7 8 90 1 2 3 45 6 7 8 9 01 2 3 4 5 67 8 DRVDEN0 INDEX# MOA# DSB# VCC DSA# MOB# DIR# STEP# WD# WE# TRAK0# WP# RDATA# HEAD# DSKCHG# CLKIN# GND PCICLK LDRQ# SERIRQ VCC3 LAD3 LAD2 LAD1 LAD0 LFRAME# LRESET# SLCT PE BUSY ACK# ERR# SLIN# PD7 PD6 PD5 PD4 -6- Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 1.0 PIN DESCRIPTION Note: Please refer to Section 13.2 DC CHARACTERISTICS for details. I/O8t - TTL level bi-directional pin with 8 mA source-sink capability I/O16t I/O12 ts I/O16ts I/O24cs I/OD16t - TTL level bi-directional pin with 16 mA source-sink capability - TTL level output pin with 12 mA source-sink capability and Schmitt-trigger input pin - TTL level output pin with 16 mA source-sink capability and Schmitt-trigger input pin - TTL level output pin with 24 mA source-sink capability and CMOS level Schmitt-trigger input pin - TTL level open-drain output pin with 16 mA source-sink capability and input pin I/OD24cs - TTL level open-drain output pin with 24 mA source-sink capability and CMOS level Schmitt-trigger input pin I/O24tp3 - 3.3V TTL level bi-directional pin with 24 mA source-sink capability O16 - Output pin with 16 mA source-sink capability O24 - Output pin with 24 mA source-sink capability OD8 - Open-drain output pin with 8 mA sink capability OD16 OD20 OD24 O24p3 INt - Open-drain output pin with 16 mA sink capability - Open-drain output pin with 20 mA sink capability - Open-drain output pin with 24 mA sink capability - 3.3V output pin with 24 mA source-sink capability - TTL level input pin INts - TTL level Schmitt -trigger input pin INcs - CMOS level Schmitt-trigger input pin INtsp3 - 3.3V TTL level Schmitt-trigger input pin 1.1 LPC Interface SYMBOL CLKIN PME# PCICLK LDRQ# SERIRQ LAD[3:0] LFRAME# PIN 17 98 19 20 21 23-26 27 I/O INt OD16 INtsp3 O24p3 I/O24tp3 I/O24tp3 INtsp3 FUNCTION System clock input. According to the input frequency 24MHz or 48MHz, it is selectable through register. Default is 24MHz input. Generated PME event. PCI clock input. Encoded DMA Request signal. Serial IRQ input/Output. These signal lines communicate address, control, and data information over the LPC bus between a host and a peripheral. Indicates start of a new cycle or termination of a broken cycle. -7- Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY LRESET# 28 INtsp3 Reset signal. It can connect to PCIRST# signal on the host. -8- Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 1.2 FDC Interface SYMBOL DRVDEN0 INDEX# PIN 1 2 I/O OD24 INcs Drive Density Select bit 0. This Schmitt-triggered input from the disk drive is active low when the head is positioned over the beginning of a track marked by an index hole. This input pin is pulled up internally by a 1 K resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). Motor A On. When set to 0, this pin enables disk drive 0. This is an open drain output. Drive Select B. When set to 0, this pin enables disk drive B. This is an open drain output. Drive Select A. When set to 0, this pin enables disk drive A. This is an open drain output. Motor B On. When set to 0, this pin enables disk drive 1. This is an open drain output. Direction of the head step motor. An open drain output. Logic 1 = outward motion Logic 0 = inward motion STEP# WD# WE# TRAK0# 9 10 11 12 OD24 OD24 OD24 INcs Step output pulses. This active low open drain output produces a pulse to move the head to another track. Write data. This logic low open drain writes pre-compensation serial data to the selected FDD. An open drain output. Write enable. An open drain output. Track 0. This Schmitt-triggered input from the disk drive is active low when the head is positioned over the outermost track. This input pin is pulled up internally by a 1 K resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). Write protected. This active low Schmitt input from the disk drive indicates that the diskette is write-protected. This input pin is pulled up internally by a 1 K resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). The read data input signal from the FDD. This input pin is pulled up internally by a 1 K resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). FUNCTION MOA# DSB# DSA# MOB# DIR# 3 4 6 7 8 OD24 OD24 OD24 OD24 OD24 WP# 13 INcs RDATA# 14 INcs -9- Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 1.2 FDC Interface, continued SYMBOL HEAD# PIN 15 I/O OD24 DSKCHG# 16 INcs FUNCTION Head select. This open drain output determines which disk drive head is active. Logic 1 = side 0 Logic 0 = side 1 Diskette change. This signal is active low at power on and whenever the diskette is removed. This input pin is pulled up internally by a 1 K resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). 1.3 Multi-Mode Parallel Port The following pins have alternate functions, which are controlled by CR28 and L3-CRF0. SYMBOL SLCT PIN 29 I/O INt FUNCTION PRINTER MODE: An active high input on this pin indicates that the printer is selected. This pin is pulled high internally. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: WE2# This pin is for Extension FDD B; its function is the same as the WE# pin of FDC. EXTENSION 2FDD MODE: WE2# This pin is for Extension FDD A and B; its function is the same as the WE# pin of FDC. PRINTER MODE: An active high input on this pin indicates that the printer has detected the end of the paper. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: WD2# This pin is for Extension FDD B; its function is the same as the WD# pin of FDC. EXTENSION 2FDD MODE: WD2# This pin is for Extension FDD A and B; its function is the same as the WD# pin of FDC. OD12 OD12 PE 30 INt OD12 OD12 - 10 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 1.3 Multi-Mode Parallel Port, continued SYMBOL BUSY PIN 31 I/O INt OD12 FUNCTION PRINTER MODE: An active high input indicates that the printer is not ready to receive data. This pin is pulled high internally. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: MOB2# This pin is for Extension FDD B; its function is the same as the MOB# pin of FDC. EXTENSION 2FDD MODE: MOB2# This pin is for Extension FDD A and B; its function is the same as the MOB# pin of FDC. PRINTER MODE: ACK# An active low input on this pin indicates that the printer has received data and is ready to accept more data. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: DSB2# This pin is for the Extension FDD B; its functions is the same as the DSB# pin of FDC. EXTENSION 2FDD MODE: DSB2# This pin is for Extension FDD A and B; its function is the same as the DSB# pin of FDC. PRINTER MODE: ERR# An active low input on this pin indicates that the printer has encountered an error condition. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: HEAD2# This pin is for Extension FDD B; its function is the same as the HEAD#pin of FDC. EXTENSION 2FDD MODE: HEAD2# This pin is for Extension FDD A and B; its function is the same as the HEAD# pin of FDC. OD12 ACK# 32 INt OD12 OD12 ERR# 33 INt OD12 OD12 - 11 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 1.3 Multi-Mode Parallel Port, continued SYMBOL SLIN# PIN 34 I/O OD12 OD12 OD12 INIT# 43 OD12 OD12 OD12 AFD# 44 OD12 OD12 OD12 FUNCTION PRINTER MODE: SLIN# Output line for detection of printer selection. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: STEP2# This pin is for Extension FDD B; its function is the same as the STEP# pin of FDC. EXTENSION 2FDD MODE: STEP2# This pin is for Extension FDD A and B; its function is the same as the STEP# pin of FDC. PRINTER MODE: INIT# Output line for the printer initialization. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: DIR2# This pin is for Extens ion FDD B; its function is the same as the DIR# pin of FDC. EXTENSION 2FDD MODE: DIR2# This pin is for Extension FDD A and B; its function is the same as the DIR# pin of FDC. PRINTER MODE: AFD# An active low output from this pin causes the printer to auto feed a line after a line is printed. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: DRVDEN0 This pin is for Extension FDD B; its function is the same as the DRVDEN0 pin of FDC. EXTENSION 2FDD MODE: DRVDEN0 This pin is for Extension FDD A and B; its function is the same as the DRVDEN0 pin of FDC. - 12 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 1.3 Multi-Mode Parallel Port, continued SYMBOL STB# PIN 46 I/O OD12 PD0 42 I/O12t INt INt PD1 41 I/O12t INt INt PD2 40 I/O12t INt INt FUNCTION PRINTER MODE: STB# An active low output is used to latch the parallel data into the printer. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION 2FDD MODE: This pin is a tri-state output. PRINTER MODE: PD0 Parallel port data bus bit 0. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: INDEX2# This pin is for Extension FDD B; its function is the same as the INDEX# pin of FDC. It is pulled high internally. EXTENSION 2FDD MODE: INDEX2# This pin is for Extension FDD A and B; its function is the same as the INDEX# pin of FDC. It is pulled high internally. PRINTER MODE: PD1 Parallel port data bus bit 1. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: TRAK02# This pin is for Extension FDD B; its function is the same as the TRAK0# pin of FDC. It is pulled high internally. EXTENSION. 2FDD MODE: TRAK02# This pin is for Extension FDD A and B; its function is the same as the TRAK0# pin of FDC. It is pulled high internally. PRINTER MODE: PD2 Parallel port data bus bit 2. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: WP2# This pin is for Extension FDD B; its function is the same as the WP# pin of FDC. It is pulled high internally. EXTENSION. 2FDD MODE: WP2# This pin is for Extension FDD A and B; its function is the same as the WP# pin of FDC. It is pulled high internally. - 13 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 1.3 Multi-Mode Parallel Port, continued SYMBOL PD3 PIN 39 I/O I/O12t INt INt PD4 38 I/O12t INt INt PD5 37 I/O12t PD6 36 I/OD12t OD12 PD7 35 I/OD12t OD12 FUNCTION PRINTER MODE: PD3 Parallel port data bus bit 3. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: RDATA2# This pin is for Extension FDD B; its function is the same as the RDATA# pin of FDC. It is pulled high internally. EXTENSION 2FDD MODE: RDATA2# This pin is for Extension FDD A and B; its function is the same as the RDATA# pin of FDC. It is pulled high internally. PRINTER MODE: PD4 Parallel port data bus bit 4. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: DSKCHG2# This pin is for Extension FDD B; the function of this pin is the same as the DSKCHG# pin of FDC. It is pulled high internally. EXTENSION 2FDD MODE: DSKCHG2# This pin is for Extension FDD A and B; this function of this pin is the same as the DSKCHG# pin of FDC. It is pulled high internally. PRINTER MODE: PD5 Parallel port data bus bit 5. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION 2FDD MODE: This pin is a tri-state output. PRINTER MODE: PD6 Parallel port data bus bit 6. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION. 2FDD MODE: MOA2# This pin is for Extension FDD A; its function is the same as the MOA# pin of FDC. PRINTER MODE: PD7 Parallel port data bus bit 7. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION 2FDD MODE: DSA2# This pin is for Extension FDD A; its function is the same as the DSA# pin of FDC. - 14 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 1.4 Serial Port Interface SYMBOL CTSA# CTSB# DSRA# DSRB# RTSA# HEFRAS PIN 47 55 48 56 49 I/O INt FUNCTION Clear To Send. It is the modem control input. The function of these pins can be tested by reading bit 4 of the handshake status register. Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. UART A Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. During power-on reset, this pin is pulled down internally and is defined as HEFRAS, which provides the power-on value for CR26 bit 6 (HEFRAS). A 4.7 k is recommended if intends to pull up. (select 4EH as configuration I/O ports address) UART B Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. UART A Data Terminal Ready. An active low signal informs the modem or data set that the controller is ready to communicate. During power-on reset, this pin is pulled down internally and is defined as PNPCSV#, which provides the power-on value for CR24 bit 0 (PNPCSV#). A 4.7 k is recommended if intends to pull up. (clear the default value of FDC, UARTs, and PRT) UART B Data Terminal Ready. An active low signal informs the modem or data set that controller is ready to communicate. Serial Input. It is used to receive serial data through the communication link. UART A Serial Output. It is used to transmit serial data out to the communication link. During power on reset , this pin is pulled down internally and is defined as PENROM#, which provides the power on value for CR24 bit 1. A 4.7k is recommended if intends to pull up . UART B Serial Output. During power-on reset, this pin is pulled down internally and is defined as PEN48, which provides the poweron value for CR24 bit 6 (EN48). A 4.7 k resistor is recommended if intends to pull up. Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. Ring Indicator. An active low signal indicates that a ring signal is being received from the modem or data set. INt I/O8t RTSB# DTRA# PNPCSV# 57 50 I/O8t I/O8t DTRB# SINA SINB SOUTA PENROM# SOUTB PEN48 58 51 59 52 I/O8t INt I/O8t 61 I/O8t DCDA# DCDB# RIA# RIB# 53 62 54 63 INt INt - 15 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 1.5 Infrared Port SYMBOL IRRX IRTX PIN 64 65 I/O INts FUNCTION Alternate Function Input: Infrared Receiver input. General purpose I/O port 3 bit 6. Alternate Function Output: Infrared Transmitter Output. General purpose I/O port 3 bit 7. OUT12t 1.6 Fresh ROM Interface SYMBOL XA18-XA16 GP57-GP55 XA15-XA10 GP47-GP42 XA9-XA8 GP41-GP40 XA7-XA0 GP37-GP30 XD7-XD4 GP27-GP24 XD3-XD0 GP23-GP20 ROMCS# GP54 MEMR# GP53 MEMW# GP52 97 96 95 91-94 86-89 78-85 76-77 69-74 PIN 66-68 I/O O I/OD12t O I/OD12t O I/OD12t O I/OD12t O I/OD12t O I/OD12t O I/OD12t O I/OD12t O I/OD12t FUNCTION Flash ROM interface Address[18:16] General purpose I/O port 5 bit7-5 Flash ROM interface Address[15:10] General purpose I/O port 4 bit7-2 Flash ROM interface Address[9:8] General purpose I/O port 4 bit1-0 Flash ROM interface Address[7:0] General purpose I/O port 3 bit7-0 Flash ROM interface Data Bus[7:4] General purpose I/O port 2 bit7-4 Flash ROM interface Data Bus [3:0] General purpose I/O port 2 bit3-0 Flash ROM interface Chip Select General purpose I/O port 5 bit4 Flash ROM interface Memory Read Enable General purpose I/O port 5 bit3 Flash ROM interface Memory Write Enable General purpose I/O port 5 bit2 - 16 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 1.7 General Purpose I/O Port SYMBOL GP73 GP80 WDTO GP67 GP66 GP65 GP64 GP63 GP62 GP61 GP60 99 100 101 102 103 104 105 106 PIN 111 118 I/O I/OD12t I/OD12t OD12 I/OD12t I/OD12t I/OD12t I/OD12t I/OD12t I/OD12t I/OD12t I/OD12t FUNCTION General purpose I/O port 7 bit3 General purpose I/O port 8 bit0 Watch dog timer output. General purpose I/O port 6 bit7. General purpose I/O port 6 bit6. General purpose I/O port 6 bit5. General purpose I/O port 6 bit4. General purpose I/O port 6 bit3. General purpose I/O port 6 bit2. General purpose I/O port 6 bit1. General purpose I/O port 6 bit0. 1.8 Smart Card Interface SYMBOL SCPSNT GP77 SCIO GP76 SCCLK GP75 SCRST GP74 SCC8 GP72 SCPWR GP71 SCC4 GP70 108 109 110 112 113 114 PIN 107 I/O INts FUNCTION Smart card present detection Schmitt-trigger input. General purpose I/O port 7 bit7. Smart card data I/O channel. General purpose I/O port 7 bit6. Smart card clock output. General purpose I/O port 7 bit5. Smart card reset output. General purpose I/O port 7 bit4. Smart card General Purpose I/O channel. General purpose I/O port 7 bit2. Smart card power control. General purpose I/O port 7 bit1. Smart card General Purpose I/O channel. General purpose I/O port 7 bit0. I/OD12t I/O12t I/OD12t OUT12 I/OD12t OUT12 I/OD12t I/O12t I/OD12t OUT12 I/OD12t I/O12t I/OD12t - 17 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 1.9 PWM & General Purpose I/O Port 8 SYMBOL PWM2 PLED GP83 PWM1-0 GP82-81 116117 PIN 115 I/O OUT16t FUNCTION Fan speed control . Use the Pulse Width Modulation (PWM) Power LED output, this signal is low after system reset. General purpose I/O port 8 bit2-1 Fan speed control . Use the Pulse Width Modulation (PWM) Technic knowledge to control the Fan's RPM. General purpose I/O port 8 bit2-1 OD12 I/OD12t OUT16t I/OD12t 1.10 Game Port & MIDI Port SYMBOL MSI GP51 MSO GP50 GPAS2 GP17 GPBS2 GP16 GPAY GP15 GPBY GP14 124 123 122 120 121 PIN 119 I/O INt I/OD12 OUT12t I/OD12 INcs I/OD12 INcs I/OD12 I/OD12 I/OD12 I/OD12 I/OD12 MIDI serial data input . General purpose I/O port 5 bit 1. MIDI serial data output. General purpose I/O port 5 bit 0. Active-low, Joystick I switch input 2. This pin has an internal pull-up resistor. (Default) General purpose I/O port 1 bit 7. Active-low, Joystick II switch input 2. This pin has an internal pull-up resistor. (Default) General purpose I/O port 1 bit 6. Joystick I timer pin. this pin connect to Y positioning variable resistors for the Josystick. (Default) General purpose I/O port 1 bit 5. Joystick II timer pin. this pin connect to Y positioning variable resistors for the Josystick. (Default) General purpose I/O port 1 bit 4. FUNCTION - 18 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 1.10 Game Port & MIDI Port, continued SYMBOL GPBX GP13 GPAX GP12 GPBS1 GP11 GPAS1 GP10 PIN 125 I/O I/OD12 I/OD12 FUNCTION Joystick II timer pin. this pin connect to X positioning variable resistors for the Josystick. (Default) General purpose I/O port 1 bit 3. Joystick I timer pin. this pin connect to X positioning variable resistors for the Josystick. (Default) General purpose I/O port 1 bit 2. Active-low, Joystick II switch input 1. This pin has an internal pull-up resistor. (Default) General purpose I/O port 1 bit 1. Active-low, Joystick I switch input 1. This pin has an internal pull-up resistor. (Default) General purpose I/O port 1 bit 0. 126 I/OD12 I/OD12 127 INcs I/OD12 128 INcs I/OD12 1.11 POWER PINS SYMBOL VCC VCC3V GND PIN 5, 45, 75, 22 18, 60, 90, FUNCTION +5V power supply for the digital circuitry. +3.3V power supply for driving 3V on host interface. Ground. - 19 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 2.0 LPC (LOW PIN COUNT) INTERFACE LPC interface is to replace ISA interface serving as a bus interface between host (chip-set) and peripheral (Winbond I/O). Data transfer on the LPC bus are serialized over a 4 bit bus. The general characteristics of the interface implemented in Winbond LPC I/O are: * * * * * * * One control line, namely LFRAME#, which is used by the host to start or stop transfers. peripherals drive this signal. No The LAD[3:0] bus, which communicates information serially. The information conveyed are cycle type, cycle direction, chip selection, address, data, and wait states. MR (master reset) of Winbond ISA I/O is replaced with a active low reset signal, namely LRESET#, in Winbond LPC I/O. An additional 33 MHz PCI clock is needed in Winbond LPC I/O for synchronization. DMA requests are issued through LDRQ#. Interrupt requests are issued through SERIRQ. Power management events are issued through PME#. Comparing to its ISA counterpart, LPC implementation saves up to 40 pin counts free for integrating more devices on a single chip. The transition from ISA to LPC is transparent in terms of software which means no BIOS or device driver update is needed except chip-specific configuration. - 20 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 3.0 FDC FUNCTIONAL DESCRIPTION 3.1 W83697SF FDC The floppy disk controller of the W83697SF integrates all of the logic required for floppy disk control. The FDC implements a PC/AT or PS/2 solution. All programmable options default to compatible values. The FIFO provides better system performance in multi-master systems. The digital data separator supports up to 2 M bits/sec data rate. The FDC includes the following blocks: AT interface, Precompensation, Data Rate Selection, Digital Data Separator, FIFO, and FDC Core. 3.1.1 AT interface The interface consists of the standard asynchronous signals: RD# , WR#, A0-A3, IRQ, DMA control, and a data bus. The address lines select between the configuration registers, the FIFO and control/status registers. This interface can be switched between PC/AT, Model 30, or PS/2 normal modes. The PS/2 register sets are a superset of the registers found in a PC/AT. 3.1.2 FIFO (Data) The FIFO is 16 bytes in size and has programmable threshold values. All command parameter information and disk data transfers go through the FIFO. Data transfers are governed by the RQM a nd DIO bits in the Main Status Register. The FIFO defaults to disabled mode after any form of reset. This maintains PC/AT hardware compatibility. The default values can be changed through the CONFIGURE command. The advantage of the FIFO is that it allows the system a larger DMA latency without causing disk errors. The following tables give several examples of the delays with a FIFO. The data are based upon the following formula: THRESHOLD # x (1/DATA/RATE) *8 - 1.5 S = DELAY FIFO THRESHOLD 1 Byte 2 Byte 8 Byte 15 Byte FIFO THRESHOLD 1 Byte 2 Byte 8 Byte 15 Byte MAXIMUM DELAY TO SERVICING AT 500K BPS Data Rate 1 x 16 S - 1.5 S = 14.5 S 2 x 16 S - 1.5 S = 30.5 S 8 x 16 S - 1.5 S = 6.5 S 15 x 16 S - 1.5 S = 238.5 S MAXIMUM DELAY TO SERVICING AT 1M BPS Data Rate 1 x 8 S - 1.5 S = 6.5 S 2 x 8 S - 1.5 S = 14.5 S 8 x 8 S - 1.5 S = 62.5 S 15 x 8 S - 1.5 S = 118.5 S - 21 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY At the start of a command the FIFO is always disabled and command parameters must be sent based upon the RQM and DIO bit settings in the main status register. When the FDC enters the command execution phase, it clears the FIFO of any data to ensure that invalid data are not transferred. An overrun and underrun will terminate the current command and the data transfer. Disk writes will complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so that the result phase may be entered. DMA transfers are enabled with the SPECIFY command and are initiated by the FDC by activating the DRQ pin during a data transfer command. The FIFO is enabled directly by asserting DACK# and addresses need not be valid. Note that if the DMA controller is programmed to function in verify mode a pseudo read is performed by the FDC based only on DACK#. This mode is only available when the FDC has been configured into byte mode (FIFO di sabled) and is programmed to do a read. With the FIFO enabled the above operation is performed by using the new VERIFY command. No DMA operation is needed. 3.1.3 Data Separator The function of the data separator is to lock onto the i ncoming serial read data. When a lock is achieved the serial front end logic of the chip is provided with a clock which is synchronized to the read data. The synchronized clock, called the Data Window, is used to internally sample the serial data portion of the bit cell, and the alternate state samples the clock portion. Serial to parallel conversion logic separates the read data into clock and data bytes. The Digital Data Separator (DDS) has three parts: control logic, error adjustment, and speed tracking. The DDS circuit cycles once every 12 clock cycles ideally. Any data pulse input will be synchronized and then adjusted by immediate error adjustment. The control logic will generate RDD and RWD for every pulse input. During any cycle where no data pulse is present, the DDS cycles are based on speed. A digital integrator is used to keep track of the speed changes in the input data stream. 3.1.4 Write Precompensation The write precompensation logic is used to minimize bit shifts in the RDDATA stream from the disk drive. Shifting of bits is a known phenomenon in magnetic media and is dependent on the disk media and the floppy drive. The FDC monitors the bit stream that is being sent to the drive. The data patterns that require precompensation are well known. Depending upon the pattern, the bit is shifted either early or late relative to the surrounding bits. - 22 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 3.1.5 Perpendicular Recording Mode The FDC is also capable of interfacing directly to perpendicular recording floppy drives. Perpendicular recording differs from the traditional longitudinal method in that the magnetic bits are oriented vertically. This scheme packs more data bits into the same area. FDCs with perpendicular recording drives can read standard 3.5" floppy disks and can read and write perpendicular media. Some manSFacturers offer drives that can read and write standard and perpendicular media in a perpendicular media drive. A single command puts the FDC into perpendicular mode. All other commands operate as they normally do. The perpendicula r mode requires a 1 Mbps data rate for the FDC. At this data rate the FIFO eases the host interface bottleneck due to the speed of data transfer to or from the disk. 3.1.6 FDC Core The W83697SF FDC is capable of performing twenty commands. Each command is initiated by a multibyte transfer from the microprocessor. The result can also be a multi-byte transfer back to the microprocessor. Each command consists of three phases: command, execution, and result. Command The microprocessor issues all required information to the controller to perform a specific operation. Execution The controller performs the specified operation. Result After the operation is completed, status information and other housekeeping information is provided to the microprocessor. 3.1.7 FDC Commands Command Symbol Descriptions: C: Cylinder number 0 - 256 D: DIR: Data Pattern Step Direction DIR = 0, step out DIR = 1, step in Disk Drive Select 0 Disk Drive Select 1 Data Length Enable Count End of Track Enable FIFO Enable Implied Seek DS0: DS1: DTL: EC: EOT: EFIFO: EIS: - 23 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY EOT: FIFOTHR: GAP: GPL: H: HDS: HLT: HUT: LOCK: MFM: MT: N: NCN: ND: OW: PCN: POLL: PRETRK: R: RCN: R/W: SC: SK: SRT: ST0: ST1: ST2: ST3: WG: End of track FIFO Threshold Gap length selection Gap Length Head number Head number select Head Load Time Head Unload Time Lock EFIFO, FIFOTHR, PTRTRK bits prevent affected by software reset MFM or FM Mode Multitrack The number of data bytes written in a sector New Cylinder Number Non-DMA Mode Overwritten Present Cylinder Number Polling Disable Precompensation Start Track Number Record Relative Cylinder Number Read/Write Sector/per cylinder Skip deleted data address mark Step Rate Time Status Register 0 Status Register 1 Status Register 2 Status Register 3 Write gate alters timing of WE - 24 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY (1) Read Data PHASE Command R/W W W W W W W W W W Execution Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N -----------------------Sector ID information after command execution D7 MT MFM 0 0 D6 SK 0 D5 0 0 D4 0 0 D3 1 1 D2 0 D1 D0 REMARKS Command codes Sector ID information prior to command execution HDS DS1 DS0 ---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL ----------------------- Data transfer between the FDD and system Status information after command execution - 25 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY (2) Read Deleted Data PHASE Command R/W W W W W W W W W W Execution Result R R R R R R R D7 D6 D5 SK 0 D4 0 0 D3 1 0 D2 1 D1 0 D0 0 REMARKS Command codes MT MFM 0 0 HDS DS1 DS0 Sector ID information prior to command execution ---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL ----------------------- Data transfer between the FDD and system -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N -----------------------Sector ID information after command execution Status information after command execution - 26 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY (3) Read A Track PHASE Command R/W W W W W W W W W W Execution D7 0 0 D6 MFM 0 D5 0 0 D4 0 0 D3 0 0 D2 0 D1 1 D0 0 REMARKS Command codes HDS DS1 DS0 Sector ID information prior to command execution ---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL ----------------------- Data transfer between the FDD and system; FDD reads contents of all cylinders from index hole to EOT R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N -----------------------Sector ID information after command execution Status information after command execution Result - 27 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY (4) Read ID PHASE Command Execution R/W W W D7 0 0 D6 MFM 0 D5 0 0 D4 0 0 D3 1 0 D2 0 D1 1 D0 0 REMARKS Command codes The first correct ID information on the cylinder is stored in Data Register R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N -----------------------Disk status after the command has been completed Status information after command execution HDS DS1 DS0 Result - 28 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY (5) Verify PHASE Command R/W W W W W W W W W Execution Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N -----------------------Sector ID information after command execution D7 EC D6 0 D5 0 D4 1 0 D3 0 0 D2 1 D1 1 D0 0 REMARKS Command codes Sector ID information prior to command execution MT MFM SK HDS DS1 DS0 ---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL/SC ------------------- No data transfer takes place Status information after command execution - 29 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY (6) Version PHASE Command Result (7) Write Data PHASE Command R/W W W W W W W W W W Execution Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N -----------------------Sector ID information after Command execution D7 0 D6 0 D5 0 0 D4 0 0 D3 0 0 D2 1 D1 0 D0 1 REMARKS Command codes Sector ID information prior to Command execution R/W W R D7 0 1 0 0 D6 0 0 D5 1 1 D4 0 0 D3 0 0 0 0 D2 0 0 D1 D0 REMARKS Command code Enhanced controller MT MFM HDS DS1 DS0 ---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL ----------------------- Data transfer between the FDD and system Status information after Command execution - 30 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY (8) Write Deleted Data PHASE Command R/W W W W W W W W W W Execution Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N -----------------------Sector ID information after command execution D7 0 D6 0 D5 0 0 D4 0 0 D3 1 0 D2 0 D1 0 D0 1 REMARKS Command codes Sector ID information prior to command execution MT MFM HDS DS1 DS0 ---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL ----------------------- Data transfer between the FDD and system Status information after command execution - 31 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY (9) Format A Track PHASE Command R/W W W W W W W Execution for Each Sector Repeat: Result W W W W R R R R R R R D7 0 0 D6 MFM 0 D5 0 0 D4 0 0 D3 1 0 D2 1 D1 0 D0 1 REMARKS Command codes Bytes/Sector Sectors/Cylinder Gap 3 Filler Byte Input Sector Parameters HDS DS1 DS0 ---------------------- N -------------------------------------------- SC ------------------------------------------- GPL ------------------------------------------ D --------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------- Undefined ---------------------------------- Undefined ---------------------------------- Undefined ---------------------------------- Undefined ------------------- Status information after command execution (10) Recalibrate PHASE Command Execution R/W W W D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 1 0 D1 1 D0 1 REMARKS Command codes Head retracted to Track 0 Interrupt DS1 DS0 (11) Sense Interrupt Status PHASE Command Result R/W W R R D7 0 D6 0 D5 0 D4 0 D3 1 D2 0 D1 0 D0 REMARKS 0 Command code Status information at the end of each seek operation ---------------- ST0 ---------------------------------------- PCN ------------------------- - 32 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY (12) Specify PHASE Command R/W W W W D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 1 D0 1 REMARKS Command codes | ---------SRT ----------- | --------- HUT ---------- | |------------ HLT ----------------------------------| ND (13) Seek PHASE Command R/W W W W Execution R D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 1 0 D2 1 D1 1 D0 1 REMARKS Command codes HDS DS1 DS0 Head positioned over proper cylinder on diskette -------------------- NCN ----------------------- (14) Configure PHASE Command R/W W W W W Execution D7 0 0 0 D6 0 0 D5 0 0 D4 1 0 D3 0 0 D2 0 0 D1 1 0 D0 1 0 REMARKS Configure information EIS EFIFO POLL | ------ FIFOTHR ----| Internal registers written | --------------------PRETRK ----------------------- | (15) Relative Seek PHASE Command R/W W W W D7 1 0 D6 DIR 0 D5 0 0 D4 0 0 D3 1 0 D2 1 D1 1 D0 1 REMARKS Command codes HDS DS1 DS0 | -------------------- RCN ---------------------------- | - 33 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY (16) Dumpreg PHASE Command Result R/W W R R R R R R R R R R (17) Perpendicular Mode PHASE Command R/W W W (18) Lock PHASE Command Result R/W W R D7 D6 D5 0 0 D4 1 LOCK D3 0 0 D2 1 0 D1 0 0 D0 0 0 REMARKS Command Code D7 0 OW D6 0 0 D5 0 D3 D4 1 D2 D3 0 D1 D2 0 D1 1 D0 0 REMARKS Command Code D7 0 D6 0 D5 0 D4 0 D3 1 D2 1 D1 1 D0 0 REMARKS Registers placed in FIFO ----------------------- PCN-Drive 0------------------------------------------ PCN-Drive 1 ----------------------------------------- PCN-Drive 2------------------------------------------ PCN-Drive 3 --------------------------SRT ------------------ | --------- HUT ------------------ HLT -----------------------------------| ND ------------------------ SC/EOT ---------------------LOCK 0 D3 D2 D1 D0 GAP WG 0 EIS EFIFO POLL | ------ FIFOTHR ------------------------------PRETRK ------------------------- D0 GAP WG LOCK 0 0 0 (19) Sense Drive Status PHASE Command Result R/W W W R D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 D2 D1 D0 REMARKS Command Code Status information about disk drive 0 1 0 0 0 HDS DS1 DS0 ---------------- ST3 ------------------------- (20) Invalid PHASE Command R/W W D7 D6 D5 D4 D3 D2 D1 D0 ------------- Invalid Codes ----------------REMARKS Invalid codes (no operationFDC goes to standby state) - 34 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY Result R -------------------- ST0 ---------------------ST0 = 80H - 35 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 3.2 Register Descriptions There are several status, data, and control registers in W83697SF. These registers are defined below: ADDRESS OFFSET base address + 0 base address + 1 base address + 2 base address + 3 base address + 4 base address + 5 base address + 7 READ SA REGISTER SB REGISTER TD REGISTER MS REGISTER DT (FIFO) REGISTER DI REGISTER DO REGISTER TD REGIS TER DR REGISTER DT (FIFO) REGISTER CC REGISTER REGISTER WRITE 3.2.1 Status Register A (SA Register) (Read base address + 0) This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode, the bit definitions for this register are as follows: 7 6 5 4 3 2 1 0 DIR WP INDEX HEAD TRAK0 STEP DRV2 INIT PENDING INIT PENDING (Bit 7): This bit indicates the value of the floppy disk interrupt output. DRV2# (Bit 6): 0 1 A second drive has been installed A second drive has not been installed STEP (Bit 5): This bit indicates the complement of STEP# output. TRAK0# (Bit 4): Publication Release Date: April 2001 Revision 0.51 - 36 - W83697SF PRELIMINARY This bit indicates the value of TRAK0# input. HEAD (Bit 3): This bit indicates the complement of HEAD# output. 0 1 side 0 side 1 INDEX# (Bit 2): This bit indicates the value of INDEX# output. WP# (Bit 1): 0 1 disk is write-protected disk is not write-protected DIR (Bit 0) This bit indicates the direction of head movement. 0 1 outward direction inward direction In PS/2 Model 30 mode, the bit definitions for this register are as follows: 7 6 5 4 3 2 1 0 DIR WP INDEX HEAD TRAK0 STEP F/F DRQ INIT PENDING INIT PENDING (Bit 7): This bit indicates the value of the floppy disk interrupt output. DRQ (Bit 6): This bit indicates the value of DRQ output pin. STEP F/F (Bit 5): Publication Release Date: April 2001 Revision 0.51 - 37 - W83697SF PRELIMINARY This bit indicates the complement of latched STEP# output. TRAK0 (Bit 4): This bit indicates the complement of TRAK0# input. HEAD# (Bit 3): This bit indicates the value of HEAD# output. 0 1 side 1 side 0 INDEX (Bit 2): This bit indicates the complement of INDEX# output. WP (Bit 1): 0 1 disk is not write-protected disk is write-protected DIR# (Bit 0) This bit indicates the direction of head movement. 0 1 inward direction outward direction 3.2.2 Status Register B (SB Register) (Read base address + 1) This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode, the bit definitions for this register are as follows: 7 1 6 1 MOT EN A MOT EN B WE RDATA Toggle WDATA Toggle Drive SEL0 5 4 3 2 1 0 Drive SEL0 (Bit 5): This bit indicates the status of DO REGISTER bit 0 (drive select bit 0). - 38 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY WDATA Toggle (Bit 4): This bit changes state at every rising edge of the WD# output pin. RDATA Toggle (Bit 3): This bit changes state at every rising edge of the RDATA# output pin. WE (Bit 2): This bit indicates the complement of the WE# output pin. MOT EN B (Bit 1) This bit indicates the complement of the MOB# output pin. MOT EN A (Bit 0) This bit indicates the complement of the MOA# output pin. In PS/2 Model 30 mode, the bit definitions for this register are as follows: 7 6 5 4 3 2 1 0 DSC DSD WE F/F RDATA F/F WD F/F DSA DSB DRV2 DRV2# (Bit 7): 0 1 A second drive has been installed A second drive has not been installed DSB# (Bit 6): This bit indicates the status of DSB# output pin. DSA# (Bit 5): This bit indicates the status of DSA# output pin. - 39 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY WD F/F(Bit 4): This bit indicates the complement of the latched WD# output pin at every rising edge of the WD# output pin. RDATA F/F(Bit 3): This bit indicates the complement of the latched RDATA# output pin . WE F/F (Bit 2): This bit indicates the complement of latched WE# output pin. DSD# (Bit 1): 0 1 Drive D has been selected Drive D has not been selected DSC# (Bit 0): 0 1 Drive C has been selected Drive C has not been selected 3.2.3 Digital Output Register (DO Register) (Write base address + 2) The Digital Output Register is a write-only register controlling drive motors, drive selection, DRQ/IRQ enable, and FDC resetting. All the bits in this register are cleared by the MR pin. The bit definitions are as follows: 7 6 5 4 3 2 1-0 Drive Select: 00 select drive A 01 select drive B 10 select drive C 11 select drive D Floppy Disk Controller Reset Active low resets FDC DMA and INT Enable Active high enable DRQ/IRQ Motor Enable A. Motor A on when Motor Enable B. Motor B on when Motor Enable C. Motor C on when Motor Enable D. Motor D on when active active active active high high high high 3.2.4. Tape Drive Register (TD Register) (Read base address + 3) This register is used to assign a particular drive number to the tape drive support mode of the data separator. This register also holds the media ID, drive type, and floppy boot drive information of the floppy - 40 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY disk drive. In normal floppy mode, this register includes only bit 0 and 1. The bit definitions are as follows: 7 X 6 X 5 X 4 X 3 X 2 X Tape sel 0 Tape sel 1 1 0 If three mode FDD function is enabled (EN3MODE = 1 in CR9), the bit definitions are as follows: 7 6 5 4 3 2 1 0 Tape Sel 0 Tape Sel 1 Floppy boot drive 0 Floppy boot drive 1 Drive type ID0 Drive type ID1 Media ID0 Media ID1 Media ID1 Media ID0 (Bit 7, 6): Thes e two bits are read only. These two bits reflect the value of CR8 bit 3, 2. Drive type ID1 Drive type ID0 (Bit 5, 4): These two bits reflect two of the bits of CR7. Which two bits are reflected depends on the last drive selected in the DO REGISTER. Floppy Boot drive 1, 0 (Bit 3, 2): These two bits reflect the value of CR8 bit 1, 0. Tape Sel 1, Tape Sel 0 (Bit 1, 0): These two bits assign a logical drive number to the tape drive. Drive 0 is not available as a tape drive and is reserved as the floppy disk boot drive. TAPE SEL 1 0 0 1 1 TAPE SEL 0 0 1 0 1 DRIVE SELECTED None 1 2 3 - 41 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY - 42 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 3.2.5 Main Status Register (MS Register) (Read base address + 4) The Main Status Register is used to control the flow of data between the microprocessor and the controller. The bit definitions for this register are as follows: 7 6 5 4 3 2 1 0 FDD 0 Busy, (D0B = 1), FDD number 0 is in the SEEK mode. FDD 1 Busy, (D1B = 1), FDD number 1 is in the SEEK mode. FDD 2 Busy, (D2B = 1), FDD number 2 is in the SEEK mode. FDD 3 Busy, (D3B = 1), FDD number 3 is in the SEEK mode. FDC Busy, (CB). A read or write command is in the process when CB = HIGH. Non-DMA mode, the FDC is in the non-DMA mode, this bit is set only during the execution phase in non-DMA mode. Transition to LOW state indicates execution phase has ended. DATA INPUT/OUTPUT, (DIO). If DIO= HIGH then transfer is from Data Register to the processor. If DIO = LOW then transfer is from processor to Data Register. Request for Master (RQM). A high on this bit indicates Data Register is ready to send or receive data to or from the p 3.2.6 Data Rate Register (DR Register) (Write base address + 4) The Data Rate Register is used to set the transfer rate and write precompensation. The data rate of the FDC is programmed by the CC REGISTER for PC-AT and PS/2 Model 30 and PS/2 mode, and not by the DR REGISTER. The real data rate is determined by the most recent write to either of the DR REGISTER or CC REGISTER. 7 6 5 0 DRATE0 DRATE1 PRECOMP0 PRECOMP1 PRECOMP2 POWER DOWN S/W RESET 4 3 2 1 0 S/W RESET (Bit 7): This bit is the software reset bit. POWER-DOWN (Bit 6): 0 1 FDC in normal mode FDC in power-down mode PRECOMP2 PRECOMP1 PRECOMP0 (Bit 4, 3, 2): These three bits select the value of write precompensation. The following tables show the precompensation values for the combination of these bits. Publication Release Date: April 2001 Revision 0.51 - 43 - W83697SF PRELIMINARY PRECOMP 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 PRECOMPENSATION DELAY 250K - 1 Mbps Default Delays 41.67 nS 83.34 nS 125.00 nS 166.67 nS 208.33 nS 250.00 nS 0.00 nS (disabled) 2 Mbps Tape drive Default Delays 20.8 nS 41.17 nS 62.5nS 83.3 nS 104.2 nS 125.00 nS 0.00 nS (disabled) DATA RATE 250 KB/S 300 KB/S 500 KB/S 1 MB/S 2 MB/S DEFAULT PRECOMPENSATION DELAYS 125 nS 125 nS 125 nS 41.67nS 20.8 nS DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC and reduced write current control. 00 01 10 11 500 KB/S (MFM), 250 KB/S (FM), RWC = 1 300 KB/S (MFM), 150 KB/S (FM), RWC = 0 250 KB/S (MFM), 125 KB/S (FM), RWC = 0 1 MB/S (MFM), Illegal (FM), RWC = 1 The 2 MB/S data rate for Tape drive is only supported by setting 01 to DRATE1 and DRATE0 bits, as well as setting 10 to DRT1 and DRT0 bits which are two of the Configure Register CRF4 or CRF5 bits in logic device 0. Please refer to the function description of CRF4 or CRF5 and data rate table for individual data rates setting. - 44 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 3.2.7 FIFO Register (R/W base address + 5) The Data Register consists of four status registers in a stack with only one register presented to the data bus at a time. This register stores data, commands, and parameters and provides diskette-drive status information. Data bytes are passed through the data register to program or obtain results after a command. In the W83697SF, this register defaults to FIFO disabled mode after reset. The FIFO can change its value and enable its operation through the CONFIGURE command. Status Register 0 (ST0) 7-6 5 4 3 2 1-0 US1, US0 Drive Select: 00 Drive A selected 01 Drive B selected 10 Drive C selected 11 Drive D selected HD Head address: 1 Head selected 0 Head selected NR Not Ready: 1 Drive is not ready 0 Drive is ready EC Equipment Check: 1 When a fault signal is received from the FDD or the track 0 signal fails to occur after 77 step pulses 0 No error SE Seek end: 1 seek end 0 seek error IC Interrupt Code: 00 Normal termination of command 01 Abnormal termination of command 10 Invalid command issue 11 Abnormal termination because the ready signal from FDD changed state during command execution Status Register 1 (ST1) 7 6 5 4 3 2 1 0 Missing Address Mark. 1 When the FDC cannot detect the data address mark or the data address mark has been deleted. NW (Not Writable). 1 If a write Protect signal is detected from the diskette drive during execution of write data. ND (No DATA). 1 If specified sector cannot be found during execution of a read, write or verifly data. Not used. This bit is always 0. OR (Over Rum). 1 If the FDC is not serviced by the host system within a certain time interval during data transf DE (data Error).1 When the FDC detects a CRC error in either the ID field or the data field. Not used. This bit is always 0. EN (End of track). 1 When the FDC tries to access a sector beyond the final sector of a cylinder. - 45 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY Status Register 2 (ST2) 7 6 5 4 3 2 1 0 MD (Missing Address Mark in Data Field). 1 If the FDC cannot find a data address mark (or the address mark has been deleted) when reading data from the media 0 No error BC (Bad Cylinder) 1 Bad Cylinder 0 No error SN (Scan Not satisfied) 1 During execution of the Scan command 0 No error SH (Scan Equal Hit) 1 During execution of the Scan command, if the equal condition is satisfied 0 No error WC (Wrong Cylinder) 1 Indicates wrong Cylinder DD (Data error in the Data field) 1 If the FDC detects a CRC error in the data field 0 No error CM (Control Mark) 1 During execution of the read data or scan command 0 No error Not used. This bit is always 0 Status Register 3 (ST3) 7 6 5 4 3 2 1 0 US0 Unit Select 0 US1 Unit Select 1 HD Head Address TS Two-Side TO Track 0 RY Ready WP Write Protected FT Fault 3.2.8 Digital Input Register (DI Register) (Read base address + 7) The Digital Input Register is an 8-bit read-only register used for diagnostic purposes. In a PC/XT or AT only Bit 7 is checked by the BIOS. When the register is read, Bit 7 shows t e complement of h DSKCHG# , while other bits of the data bus remain in tri-state. Bit definitions are as follows: 7 6 5 4 3 2 1 0 x x x x xxx for hard disk controller x Reservedreadthe this register, these bits are in tri-state During a of DSKCHG In the PS/2 mode, the bit definitions are as follows: - 46 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 7 6 1 5 1 4 1 3 1 HIGH DENS DRATE0 DRATE1 2 1 0 DSKCHG DSKCHG (Bit 7): This bit indicates the complement of the DSKCHG# input. Bit 6-3: These bits are always a logic 1 during a read. DRATE1 DRATE0 (Bit 2, 1): These two bits select the data rate of the FDC. Refer to the DR register bits 1 and 0 for the settings corresponding to the individual data rates. HIGH DENS# (Bit 0): 0 1 500 KB/S or 1 MB/S data rate (high density FDD) 250 KB/S or 300 KB/S data rate In the PS/2 Model 30 mode, the bit definitions are as follows: 7 6 0 5 0 4 0 DRATE0 DRATE1 NOPREC DMAEN 3 2 1 0 DSKCHG DSKCHG (Bit 7): This bit indicates the status of DSKCHG# input. Bit 6-4: These bits are always a logic 1 during a read. DMAEN (Bit 3): This bit indicates the value of DO REGISTER bit 3. Publication Release Date: April 2001 Revision 0.51 - 47 - W83697SF PRELIMINARY NOPREC (Bit 2): This bit indicates the value of CC REGISTER NOPREC bit. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC. 3.2.9 Configuration Control Register (CC Register) (Write base address + 7) This register is used to control the data rate. In the PC/AT and PS/2 mode, the bit definitions are as follows: 7 6 5 4 3 2 1 0 x x x x x x DRATE0 DRATE1 X: Reserved Bit 7-2: Reserved. These bits should be set to 0. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC. In the PS/2 Model 30 mode, the bit definitions are as follows: 7 X 6 X 5 X 4 X 3 X DRATE0 DRATE1 NOPREC 2 1 0 X: Reserved Bit 7-3: Reserved. These bits should be set to 0. NOPREC (Bit 2): This bit indicates no precompensation. It has no function and can be set by software. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC. - 48 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 4.0 UART PORT 4.1 Universal Asynchronous Receiver/Transmitter (UART A, UART B) The UARTs are used to convert parallel data into serial format on the transmit side and convert serial data to parallel format on the receiver side. The serial format, in order of transmission and reception, is a start bit, followed by five to eight data bits, a parity bit (if programmed) and one, one and half (five-bit format only) or two stop bits. The UARTs are capable of handling divisors of 1 to 65535 and producing a 16x clock for driving the internal transmitter logic. Provisions are also included to use this 16x clock to drive the receiver logic. The UARTs also support the MIDI data rate. Furthermore, the UARTs also include complete modem control capability and a processor interrupt system that may be software trailed to the computing time required to handle the communication link. The UARTs have a FIFO mode to reduce the number of interrupts presented to the CPU. In each UART, there are 16-byte FIFOs for both receive and transmit mode. 4.2 Register Address 4.2.1 UART Control Register (UCR) (Read/Write) The UART Control Register controls and defines the protocol for asynchronous data communications, including data length, stop bit, parity, and baud rate selection. 7 6 5 4 3 2 1 0 Data length select bit 0 (DLS0) Data length select bit 1(DLS1) Multiple stop bits enable (MSBE) Parity bit enable (PBE) Even parity enable (EPE) Parity bit fixed enable (PBFE) Set silence enable (SSE) Baudrate divisor latch access bit (BDLAB) Bit 7 BDLAB. When this bit is set to a logical 1, designers can access the divisor (in 16-bit binary format) from the divisor latches of the baudrate generator during a read or write operation. When this bit is reset, the Receiver BSFfer Register, the Transmitter BSFfer Register, or the Interrupt Control Register can be accessed. SSE. A logical 1 forces the Serial Output (SOUT) to a silent state (a logical 0). Only IRTX is affected by this bit; the transmitter is not affected. PBFE. When PBE and PBFE of UCR are both set to a logical 1, (1) if EPE is logical 1, the parity bit is fixed as logical 0 to transmit and check. (2) if EPE is logical 0, the parity bit is fixed as logical 1 to transmit and check. Bit 6 Bit 5 - 49 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY TABLE 4-1 UART Register Bit Map Bit Number Register Address Base +0 BDLAB = 0 Receiver BSFfer Register (Read Only) RBR 0 RX Data Bit 0 1 RX Data Bit 1 2 RX Data Bit 2 3 RX Data Bit 3 4 RX Data Bit 4 5 RX Data Bit 5 6 RX Data Bit 6 7 RX Data Bit 7 +0 Transmitter BDLAB = 0 BSFfer Register (Write Only) +1 BDLAB = 0 Interrupt Control Register TBR TX Data Bit 0 TX Data Bit 1 TBR Empty Interrupt Enable (ETBREI) Interrupt Status Bit (0) RCVR FIFO Reset Data Length Select Bit 1 (DLS1) Request to Send (RTS) Overrun Error (OER) DSR Toggling (TDSR) Bit 1 Bit 1 TX Data Bit 2 USR Interrupt Enable (EUSRI) Interrupt Status Bit (1) XMIT FIFO Reset Multiple Stop Bits Enable (MSBE) Loopback RI Input Parity Bit Error (PBER) RI Falling Edge (FERI) Bit 2 Bit 2 TX Data Bit 3 HSR Interrupt Enable (EHSRI) Interrupt Status Bit (2)** DMA Mode Select Parity Bit Enable (PBE) IRQ Enable TX Data Bit 4 0 TX Data Bit 5 0 TX Data Bit 6 0 TX Data Bit 7 0 ICR RBR Data Ready Interrupt Enable (ERDRI) "0" if Interrupt Pending FIFO Enable +2 Interrupt Status Register (Read Only) UART FIFO Control Register (Write Only) UART Control Register ISR 0 0 FIFOs Enabled ** FIFOs Enabled ** +2 SFR Reserved Reversed RX RX Interrupt Interrupt Active Level Active Level (LSB) (MSB) Set Silence Enable (SSE) 0 Baudrate Divisor Latch Access Bit (BDLAB) 0 +3 UCR Data Length Select Bit 0 (DLS0) Data Terminal Ready (DTR) RBR Data Ready (RDR) Even Parity Enable (EPE) Internal Loopback Enable Silent Byte Detected (SBD) Clear to Send (CTS) Bit 4 Bit 4 Parity Bit Fixed Enable PBFE) 0 +4 Handshake Control Register UART Status Register HCR +5 USR No Stop Bit Error (NSER) DCD Toggling (TDCD) Bit 3 Bit 3 TBR Empty (TBRE) Data Set Ready (DSR) Bit 5 Bit 5 TSR Empty (TSRE) Ring Indicator (RI) Bit 6 Bit 6 RX FIFO Error Indication (RFEI) ** Data Carrier Detect (DCD) Bit 7 Bit 7 +6 Handshake Status Register User Defined Register Baudrate Divisor Latch Low Baudrate Divisor Latch High HSR CTS Toggling (TCTS) Bit 0 Bit 0 +7 +0 BDLAB = 1 +1 BDLAB = 1 UDR BLL BHL Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 *: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received. - 50 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY **: These bits are always 0 in 16450 Mode. Bit 4 EPE. This bit describes the number of logic 1's in the data word bits and parity bit only when bit 3 is programmed. When this bit is set, an even number of logic 1's are sent or checked. When the bit is reset, an odd number of logic 1's are sent or checked. PBE. When this bit is set, the position between the last data bit and the stop bit of the SOUT will be stSFfed with the parity bit at the transmitter. For the receiver, the parity bit in the same position as the transmitter will be detected. MSBE. This bit defines the number of stop bits in each serial character that is transmitted or received. (1) If MSBE is set to a logical 0, one stop bit is sent and checked. (2) If MSBE is set to a logical 1, and data length is 5 bits, one and a half stop bits are sent and checked. (3) If MSBE is set to a logical 1, and data length is 6, 7, or 8 bits, two stop bits are sent and checked. Bit 3 Bit 2 Bits 0 DLS0, DLS1. These two bits define the number of data bits that are sent or checked in each and 1 serial character. TABLE 4-2 WORD LENGTH DEFINITION DLS1 0 0 1 1 DLS0 0 1 0 1 DATA LENGTH 5 bits 6 bits 7 bits 8 bits 4.2.2 UART Status Register (USR) (Read/Write) This 8-bit register provides information about the status of the data transfer during communication. 7 6 5 4 3 2 1 0 RBR Data ready (RDR) Overrun error (OER) Parity bit error (PBER) No stop bit error (NSER) Silent byte detected (SBD) Transmitter Buffer Register empty (TBRE) Transmitter Shift Register empty (TSRE) RX FIFO Error Indication (RFEI) - 51 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY Bit 7 RFEI. In 16450 mode, this bit is always set to a logic 0. In 16550 mode, this bit is set to a logic 1 when there is at least one parity bit error, no stop bit error or silent byte detected in the FIFO. In 16550 mode, this bit is cleared by reading from the USR if there are no remaining errors left in the FIFO. TSRE. In 16450 mode, when TBR and TSR are both empty, this bit will be set to a logical 1. In 16550 mode, if the transmit FIFO and TSR are both empty, it will be set to a logical 1. Other thanthese two cases, this bit will be reset to a logical 0 TBRE. In 16450 mode, when a data character is transferred from TBR to TSR, this bit will be set to a logical 1. If ETREI of ICR is a logical 1, an interrupt will be generated to notify the CPU to write the next data. In 16550 mode, this bit will be set to a logical 1 when the transmit FIFO is empty. It will be reset to a logical 0 when the CPU writes data into TBR or FIFO. SBD. This bit is set to a logical 1 to indicate that received data are kept in silent state for a full word time, including start bit, data bits, parity bit, and stop bits. In 16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit to a logical 0. NSER. This bit is set to a logical 1 to indicate that the received data have no stop bit. In 16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit to a logical 0. PBER. This bit is set to a logical 1 to indicate that the parity bit of received data is wrong. In 16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit to a logical 0. OER. This bit is set to a logical 1 to indicate received data have been overwritten by the next received data before they were read by the CPU. In 16550 mode, it indicates the same condition instead of FIFO full. When the CPU reads USR, it will clear this bit to a logical 0. RDR. This bit is set to a logical 1 to indicate received data are ready to be read by the CPU in the RBR or FIFO. After no data are left in the RBR or FIFO, the bit will be reset to a logical 0. Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 4.2.3 Handshake Control Register (HCR) (Read/Write) This register controls the pins of the UART used for handshaking peripherals such as modem, and controls the diagnostic mode of the UART. 7 0 6 0 5 0 Data terminal ready (DTR) Request to send (RTS) Loopback RI input IRQ enable Internal loopback enable 4 3 2 1 0 - 52 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY Bit 4 When this bit is set to a logical 1, the UART enters diagnostic mode by an internal loopback, as follows: (1) SOUT is forced to logical 1, and SIN is isolated from the communication link instead of the TSR. (2) Modem output pins are set to their inactive state. (3) Modem input pins are isolated from the communication link and connect internally as DTR (bit 0 of HCR) DSR, RTS ( bit 1 of HCR) CTS , Loopback RI input ( bit 2 of HCR) RI and IRQ enable ( bit 3 of HCR) DCD . Aside from the above connections, the UART operates normally. This method allows the CPU to test the UART in a convenient way. Bit 3 Bit 2 Bit 1 Bit 0 The UART interrupt output is enabled by setting this bit to a logic 1. In the diagnostic mode this bit is internally connected to the modem control input DCD . This bit is used only in the diagnostic mode. In the diagnostic mode this bit is internally connected to the modem control input RI . This bit controls the RTS output. The value of this bit is inverted and output to RTS . This bit controls the DTR output. The value of this bit is inverted and output to DTR . 4.2.4 Handshake Status Register (HSR) (Read/Write) This register reflects the current state of four input pins for handshake peripherals such as a modem and records changes on these pins. 7 6 5 4 3 2 1 0 CTS toggling (TCTS) DSR toggling (TDSR) RI falling edge (FERI) DCD toggling (TDCD) Clear to send (CTS) Data set ready (DSR) Ring indicator (RI) Data carrier detect (DCD) Bit 7 Bit 6 Bit 5 This bit is the opposite of the DCD input. This bit is equivalent to bit 3 of HCR in loopback mode. This bit is the opposite of the RI input. This bit is equivalent to bit 2 of HCR in loopback mode. This bit is the opposite of the DSR input. This bit is equivalent to bit 0 of HCR in loopback mode. - 53 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 This bit is the opposite of the CTS input. This bit is equivalent to bit 1 of HCR in loopback mode. TDCD. This bit indicates that the DCD pin has changed state after HSR was read by the CPU. FERI. This bit indicates that the RI pin has changed from low to high state after HSR was read by the CPU. TDSR. This bit indicates that the DSR pin has changed state after HSR was read by the CPU. TCTS. This bit indicates that the CTS pin has changed state after HSR was read. 4.2.5 UART FIFO Control Register (SFR) (Write only) This register is used to control the FIFO functions of the UART. 7 6 5 4 3 2 1 0 FIFO enable Receiver FIFO reset Transmitter FIFO reset DMA mode select Reserved Reserved RX interrupt active level (LSB) RX interrupt active level (MSB) Bit 6, 7 These two bits are used to set the active level for the receiver FIFO interrupt. For example, if the interrupt active level is set as 4 bytes, once there are more than 4 data characters in the receiver FIFO, the interrupt will be activated to notify the CPU to read the data from the FIFO. TABLE 4-3 FIFO TRIGGER LEVEL BIT 7 0 0 1 1 BIT 6 0 1 0 1 RX FIFO INTERRUPT ACTIVE LEVEL (BYTES) 01 04 08 14 Bit 4, 5 Reserved Bit 3 When this bit is programmed to logic 1, the DMA mode will change from mode 0 to mode 1 if SFR bit 0 = 1. - 54 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY Bit 2 Bit 1 Bit 0 Setting this bit to a logical 1 resets the TX FIFO counter logic to initial state. This bit will clear to a logical 0 by itself after being set to a logical 1. Setting this bit to a logical 1 resets the RX FIFO counter logic to initial state. This bit will clear to a logical 0 by itself after being set to a logical 1. This bit enables the 16550 (FIFO) mode of the UART. This bit should be set to a logical 1 before other bits of SFR are programmed. 4.2.6 Interrupt Status Register (ISR) (Read only) This register reflects the UART interrupt status, which is encoded by different interrupt sources into 3 bits. 7 6 5 0 4 0 0 if interrupt pending Interrupt Status bit 0 Interrupt Status bit 1 Interrupt Status bit 2 FIFOs enabled FIFOs enabled 3 2 1 0 Bit 7, 6 These two bits are set to a logical 1 when SFR bit 0 = 1. Bit 5, 4 Bit 3 These two bits are always logic 0. In 16450 mode, this bit is 0. In 16550 mode, both bit 3 and 2 are set to a logical 1 when a time-out interrupt is pending. Bit 2, 1 These two bits identify the priority level of the pending interrupt, as shown in the table below. Bit 0 This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has occurred, this bit will be set to a logical 0. TABLE 4-4 INTERRUPT CONTROL FUNCTION ISR Bit 3 0 0 0 Bit 2 0 1 1 Bit 1 0 1 0 Bit 0 1 0 0 Interrupt priority First Second Interrupt Type UART Receive Status RBR Data Ready INTERRUPT SET AND FU NCTION Interrupt Source No Interrupt pending 1. OER = 1 2. PBER =1 Read USR 1. Read RBR 2. Read RBR until FIFO data under active level Read RBR 3. NSER = 1 4. SBD = 1 1. RBR data ready 2. FIFO interrupt active level reached Clear Interrupt - 1 1 0 0 Second FIFO Data Timeout Data present in RX FIFO for 4 characters period of time since last access of RX FIFO. - 55 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 0 0 1 0 Third TBR Empty TBR empty 1. Write data into TBR 2. Read ISR (if priority is third) 0 0 0 0 Fourth Handshake status 1. TCTS = 1 3. FERI = 1 ** Bit 3 of ISR is enabled when bit 0 of SFR is logical 1. 2. TDSR = 1 4. TDCD = 1 Read HSR - 56 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 4.2.7 Interrupt Control Register (ICR) (Read/Write) This 8-bit register allows the five types of controller interrupts to activate the interrupt output signal separately. The interrupt system can be totally disabled by resetting bits 0 through 3 of the Interrupt Control Register (ICR). A selected interrupt can be enabled by setting the appropriate bits of this register to a logical 1. 7 0 6 0 5 0 4 0 RBR data ready interrupt enable (ERDRI) TBR empty interrupt enable (ETBREI) UART receive status interrupt enable (EUSRI) Handshake status interrupt enable (EHSRI) 3 2 1 0 Bit 7-4: Bit 3 Bit 2 Bit 1 Bit 0: These four bits are always logic 0. EHSRI. Setting this bit to a logical 1 enables the handshake status register interrupt. EUSRI. Setting this bit to a logical 1 enables the UART status register interrupt. ETBREI. Setting this bit to a logical 1 enables the TBR empty interrupt. ERDRI. Setting this bit to a logical 1 enables the RBR data ready interrupt. 4.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write) Two 8-bit registers, BLL and BHL, compose a programmable baud generator that uses 24 MHz to 16 generate a 1.8461 MHz frequency and divides it by a divisor from 1 to 2 -1. The output frequency of the baud generator is the baud rate multiplied by 16, and this is the base frequency for the transmitter and receiver. The table in the next page illustrates the use of the baud generator with a frequency of 1.8461 MHz. In high-speed UART mode (refer to CR0C bit7 and CR0C bit6), the programmable baud generator directly uses 24 MHz and the same divisor as the normal speed divisor. In high-speed mode, the data transmission rate can be as high as 1.5M bps. - 57 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 4.2.9 User-defined Register (UDR) (Read/Write) This is a temporary register that can be accessed and defined by the user. TABLE 4-5 BAUD RATE TABLE BAUD RATE FROM DIFFERENT PRE-DIVIDER Pre-Div: 13 1.8461M Hz 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 57600 115200 Pre-Div:1.625 14.769M Hz 400 600 880 1076 1200 2400 4800 9600 14400 16000 19200 28800 38400 57600 76800 153600 307200 460800 921600 Pre-Div: 1.0 24M Hz 650 975 1430 1478.5 1950 3900 7800 15600 23400 26000 31200 46800 62400 93600 124800 249600 499200 748800 1497600 Decimal divisor used to generate 16X clock 2304 1536 1047 857 768 384 192 96 64 58 48 32 24 16 12 6 3 2 1 Error Percentage between desired and actual ** ** 0.18% 0.099% ** ** ** ** ** 0.53% ** ** ** ** ** ** ** ** ** ** The percentage error for all baud rates, except where indicated otherwise, is 0.16%. Note. Pre-Divisor is determined by CRF0 of UART A and B. - 58 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 5.0 PARALLEL PORT 5.1 Printer Interface Logic The parallel port of the W83627SF makes possible the attachment of various devices that accept eight bits of parallel data at standard TTL level. The W83627SF supports an IBM XT/AT compatible parallel port (SPP), bi -directional parallel port (BPP), Enhanced Parallel Port (EPP), Extended Capabilities Parallel Port (ECP), Extension FDD mode (EXTFDD), Extension 2FDD mode (EXT2FDD) on the parallel port. Refer to the configuration registers for more information on disabling, power-down, and on selecting the mode of operation. Table 6-1 shows the pin definitions for different modes of the parallel port. TABLE 6-1-1 PARALLEL PORT CONNECTOR AND PIN DEFINITIONS HOST CONNECTOR 1 2-9 10 11 12 13 14 15 16 17 Notes: n 2 BUSY, PeriphAck PEerror, nAckReverse2 SLCT, Xflag 2 nAFD, HostAck2 2 nFault1, nPeriphRequest nINIT1, nReverseRqst2 nSLIN1 , ECPMode2 - 59 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY TABLE 6-1-2 PARALLEL PORT CONNECTOR AND PIN DEFINITIONS HOST CONNECTOR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PIN NUMBER OF W83627SF 36 31 30 29 28 27 26 24 23 22 21 19 18 35 34 33 32 PIN ATTRIBUTE O I/O I/O I/O I/O I/O I/O I/O I/O I I I I O I O O SPP nSTB PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 nACK BUSY PE SLCT nAFD nERR nINIT nSLIN PIN ATTRIBUTE --I I I I I --OD OD OD OD OD OD OD OD OD OD EXT2FDD --INDEX2# TRAK02# WP2# RDATA2# DSKCHG2# --MOA2# DSA2# DSB2# MOB2# WD2# WE2# RWC2# HEAD2# DIR2# STEP2# PIN ATTRIBUTE --I I I I I ------OD OD OD OD OD OD OD OD EXTFDD --INDEX2# TRAK02# WP2# RDATA2# DSKCHG2# ------DSB2# MOB2# WD2# WE2# RWC2# HEAD2# DIR2# STEP2# 5.2 Enhanced Parallel Port (EPP) TABLE 6-2 PRINTER MODE AND EPP REGISTER ADDRESS A2 0 0 0 0 0 1 1 1 1 Notes: 1. These registers are available in all modes. 2. These registers are available only in EPP mode. A1 0 0 1 1 1 0 0 1 1 A0 0 1 0 0 1 0 1 0 1 REGISTER Data port (R/W) Printer status bSFfer (Read) Printer control latch (Write) Printer control swapper (Read) EPP address port (R/W) EPP data port 0 (R/W) EPP data port 1 (R/W) EPP data port 2 (R/W) EPP data port 2 (R/W) NOTE 1 1 1 1 2 2 2 2 2 - 60 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY - 61 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 5.2.1 Data Swapper The system microprocessor can read the contents of the printer's data latch by reading the data swapper. 5.2.2 Printer Status BSFfer The system microprocessor can read the printer status by reading the address of the printer status bSFfer. The bit definitions are as follows: 7 6 5 4 3 2 1 1 1 TMOUT ERROR SLCT PE ACK BUSY 0 Bit 7 This signal is active during data entry, when the printer is off-line during printing, when the print head is changing position, or during an error state. When this signal is active, the printer is busy and cannot accept data. This bit represents the current state of the printer's ACK# signal. A 0 means the printer has received a character and is ready to accept another. Normally, this signal will be active for approximately 5 microseconds before BUSY# stops. Logical 1 means the printer has detected the end of paper. Logical 1 means the printer is selected. Logical 0 means the printer has encountered an error condition. This bit is valid in EPP mode only. It indicates that a 10 S time-out has occurred on the EPP bus. A logic 0 means that no time-out error has occurred; a logic 1 means that a time-out error has been detected. Writing a logic 1 to this bit will clear the time-out status bit; writing a logic 0 has no effect. Bit 6 Bit 5 Bit 4 Bit 3 Bit 0 Bit 1, 2 These two bits are not implemented and are logic one during a read of the status register. 5.2.3 Printer Control Latch and Printer Control Swapper The system microprocessor can read the contents of the printer control latch by reading the printer control swapper. Bit definitions are as follows: - 62 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 7 1 6 1 STROBE AUTO FD INIT SLCT IN IRQ ENABLE DIR 5 4 3 2 1 0 Bit 7, 6 These two bits are a logic one during a read. They can be written. Bit 5 Direction control bit. When this bit is a logic 1, the parallel port is in input mode (read); when it is a logic 0, the parallel port is in output mode (write). This bit can be read and written. In SPP mode, this bit is invalid and fixed at zero. Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 A 1 in this position allows an interrupt to occur when ACK# changes from low to high. A 1 in this bit position selects the printer. A 0 starts the printer (50 microsecond pulse, minimum). A 1 causes the printer to line-feed after a line is printed. A 0.5 microsecond minimum high active pulse clocks data into the printer. Valid data must be present for a minimum of 0.5 microseconds before and after the strobe pulse. 5.2.4 EPP Address Port The address port is available only in EPP mode. Bit definitions are as follows: 7 6 5 4 3 2 1 0 MD (Missing Address Mark in Data Field). 1 If the FDC cannot find a data address mark (or the address mark has been deleted) when reading data from the media 0 No error BC (Bad Cylinder) 1 Bad Cylinder 0 No error SN (Scan Not satisfied) 1 During execution of the Scan command 0 No error SH (Scan Equal Hit) 1 During execution of the Scan command, if the equal condition is satisfied 0 No error WC (Wrong Cylinder) 1 Indicates wrong Cylinder DD (Data error in the Data field) 1 If the FDC detects a CRC error in the data field 0 No error CM (Control Mark) 1 During execution of the read data or scan command 0 No error Not used. This bit is always 0 - 63 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY The contents of DB0-DB7 are bSFfered (non-inverting) and output to ports PD0-PD7 during a write operation. The leading edge of IOW# causes an EPP address write cycle to be performed, and the trailing edge of IOW# latches the data for the duration of the EPP write cycle. PD0-PD7 ports are read during a read operation. The leading edge of IOR# causes an EPP address read cycle to be performed and the data to be output to the host CPU. 5.2.5 EPP Data Port 0-3 These four registers are available only in EPP mode. Bit definitions of each data port are as follows: 7 6 5 4 3 2 1 0 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 When accesses are made to any EPP data port, the contents of DB0-DB7 are bSFfered (non-inverting) and output to the ports PD0-PD7 during a write operation. The leading edge of IOW# causes an EPP data write cycle to be performed, and the trailing edge of IOW# latches the data for the duration of the EPP write cycle. During a read operation, ports PD0-PD7 are read, and the leading edge of IOR# causes an EPP read cycle to be performed and the data to be output to the host CPU. 5.2.6 Bit Map of Parallel Port and EPP Registers REGISTER Data Port (R/W) Status BSFfer (Read) Control Swapper (Read) Control Latch (Write) EPP Address Port R/W) EPP Data Port 0 (R/W) EPP Data Port 1 (R/W) EPP Data Port 2 (R/W) 7 PD7 BUSY# 1 1 PD7 PD7 PD7 PD7 6 PD6 ACK# 1 1 PD6 PD6 PD6 PD6 5 PD 5 PE 1 DIR PD 5 PD 5 PD 5 PD 5 4 PD4 SLCT IRQEN IRQ PD4 PD4 PD4 PD4 3 PD3 ERROF# 2 PD2 1 INIT# INIT# PD2 PD2 PD2 PD2 1 PD1 1 AUTOFD# AUTOFD# PD1 PD1 PD1 PD1 0 PD0 TMOUT STROBE# STROBE# PD0 PD0 PD0 PD0 SLIN SLIN PD3 PD3 PD3 PD3 - 64 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY EPP Data Port 3 (R/W) PD7 PD6 PD 5 PD4 PD3 PD2 PD1 PD0 - 65 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 5.2.7 EPP Pin Descriptions EPP NAME nWrite PD<0:7> Intr nWait PE Select nDStrb nError nInits nAStrb TYPE O I/O I I I I O I O O EPP DESCRIPTION Denotes an address or data read or write operation. Bi-directional EPP address and data bus. Used by peripheral device to interrupt the host. Inactive to acknowledge that data transfer is completed. Active to indicate that the device is ready for the next transfer. Paper end; same as SPP mode. Printer selected status; same as SPP mode. This signal is active low. It denotes a data read or write operation. Error; same as SPP mode. This signal is active low. When it is active, the EPP device is reset to its initial operating mode. This signal is active low. It denotes an address read or write operation. 5.2.8 EPP Operation When the EPP mode is selected in the configuration register, the standard and bi-directional modes are also available. The PDx bus is in the standard or bi-directional mode when no EPP read, write, or address cycle is currently being executed. In this condition all output signals are set by the SPP Control Port and the direction is controlled by DIR of the Control Port. A watchdog timer is required to prevent system lockup. The timer indicates that more than 10 S have elapsed from the start of the EPP cycle to the time WAIT# is deasserted. The current EPP cycle is aborted when a time-out occurs. The time-out condition is indicated in Status bit 0. 5.2.8.1 EPP Operation The EPP operates on a two-phase cycle. First, the host selects the register within the device for subsequent operations. Second, the host performs a series of read and/or write byte operations to the selected register. Four operations are supported on the EPP: Address Write, Data Write, Address Read, and Data Read. All operations on the EPP device are performed asynchronously. 5.2.8.2 EPP Version 1.9 Operation The EPP read/write operation can be completed under the following conditions: a. If the nWait is active low, when the read cycle (nWrite inactive high, nDStrb/nAStrb active low) or write cycle (nWrite active low, nDStrb/nAStrb active low) starts, the read/write cycle proceeds normally and will be completed when nWait goes inactive high. b. If nWait is inactive high, the read/write cycle will not start. It must wait until nWait changes to active low, at which time it will start as described above. 5.2.8.3 EPP Version 1.7 Operation - 66 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY The EPP read/write cycle can start without checking whether nWait is active or inactive. Once the read/write cycle starts, however, it will not terminate until nWait changes from active low to inactive high. - 67 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 5.3 Extended Capabilities Parallel (ECP) Port This port is software and hardware compatible with existing parallel ports, so it may be used as a standard printer mode if ECP is not required. It provides an automatic high burst-bandwidth channel that supports DMA for ECP in both the forward (host to peripheral) and reverse (peripheral to host) directions. Small FIFOs are used in both forward and reverse directions to improve the maximum bandwidth requirement. The size of the FIFO is 16 bytes. The ECP port supports an automatic handshake for the standard parallel port to improve compatibility mode transfer speed. The ECP port supports run -length-encoded (RLE) decompression (required) in hardware. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated. Hardware support for compression is optional. For more information about the ECP Protocol, refer to the Extended Capabilities Port Protocol and ISA Interface Standard. 5.3.1 ECP Register and Mode Definitions NAME data ecpAFifo dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr ADDRESS Base+000h Base+000h Base+001h Base+002h Base+400h Base+400h Base+400h Base+400h Base+401h Base+402h I/O R/W R/W R R/W R/W R/W R/W R R/W R/W ECP MODES 000-001 011 All All 010 011 110 111 111 All FUNCTION Data Register ECP FIFO (Address) Status Register Control Register Parallel Port Data FIFO ECP FIFO (DATA) Test FIFO Configuration Register A Configuration Register B Extended Control Register Note: The base addresses are specified by CR23, which are determined by configuration register or hardware setting. MODE 000 001 010 011 100 101 110 111 SPP mode PS/2 Parallel Port mode Parallel Port Data FIFO mode ECP Parallel Port mode DESCRIPTION EPP mode (If this option is enabled in the CR9 and CR0 to select ECP/EPP mode) Reserved Test mode Configuration mode Note: The mode selection bits are bit 7 -5 of the Extended Control Register. - 68 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 5.3.2 Data and ecpAFifo Port Modes 000 (SPP) and 001 (PS/2) (Data Port) During a write operation, the Data Register latches the contents of the data bus on the rising edge of the input. The contents of this register are output to the PD0-PD7 ports. During a read operation, ports PD0PD7 are read and output to the host. The bit definitions are as follows: 7 6 5 4 3 2 1 0 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Mode 011 (ECP FIFO -Address/RLE) A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The hardware at the ECP port transmits this byte to the peripheral automatically. The operation of this register is defined only for the forward direction. The bit definitions are as follows: 7 6 5 4 3 2 1 0 Address or RLE Address/RLE 5.3.3 Device Status Register (DSR) These bits are at low level during a read of the Printer Status Register. The bits of this status register are defined as follows: 7 6 5 4 3 2 1 1 1 0 1 nFault Select PError nAck nBusy - 69 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2-0 This bit reflects the complement of the Busy input. This bit reflects the nAck input. This bit reflects the PError input. This bit reflects the Select input. This bit reflects the nFault input. These three bits are not implemented and are always logic one during a read. 5.3.4 Device Control Register (DCR) The bit definitions are as follows: 7 6 5 4 3 2 1 0 VCOREA VCOREB +3.3VIN +5VIN TEMP1 TEMP2 FAN1 FAN2 Bit 6, 7 These two bits are logic one during a read and cannot be written. Bit 5 This bit has no effect and the direction is always out if mode = 000 or mode = 010. Direction is valid in all other modes. 0 1 Bit 4 the parallel port is in output mode. the parallel port is in input mode. Interrupt request enable. When this bit is set to a high level, it may be used to enable interrupt requests from the parallel port to the CPU due to a low to high transition on the ACK# input. This bit is inverted and output to the SLIN# output. 0 1 The printer is not selected. The printer is selected. Bit 3 Bit 2 Bit 1 Bit 0 This bit is output to the INIT# output. This bit is inverted and output to the AFD# output. This bit is inverted and output to the STB# output. - 70 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 5.3.5 cFifo (Parallel Port Data FIFO) Mode = 010 This mode is defined only for the forward direction. The standard parallel port protocol is used by a hardware handshake to the peripheral to transmit bytes written or DMAed from the system to this FIFO. Transfers to the FIFO are byte aligned. 5.3.6 ecpDFifo (ECP Data FIFO) Mode = 011 When the direction bit is 0, bytes written or DMAed from the system to this FIFO are transmitted by a hardware handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are byte aligned. When the direction bit is 1, data bytes from the peripheral are read under automatic hardware handshake from ECP into this FIFO. Reads or DMAs from the FIFO will return bytes of ECP data to the system. 5.3.7 tFifo (Test FIFO Mode) Mode = 110 Data bytes may be read, written, or DMAed to or from the system to this FIFO in any direction. Data in the tFIFO will not be transmitted to the parallel port lines. However, data in the tFIFO may be displayed on the parallel port data lines. 5.3.8 cnfgA (Configuration Register A) Mode = 111 This register is a read-only register. When it is read, 10H is returned. This indicates to the system that this is an 8-bit implementation. 5.3.9 cnfgB (Configuration Register B) Mode = 111 The bit definitions are as follows: 7 6 5 4 3 1 2 1 1 0 1 IRQx 0 IRQx 1 IRQx 2 intrValue compress Bit 7 Bit 6 Bit 5-3 This bit is read-only. It is at low level during a read. This means that this chip does not support hardware RLE compression. Returns the value on the ISA IRQ line to determine possible conflicts. Reflect the IRQ resource assigned for ECP port. - 71 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY cnfgB[5:3] 000 001 010 011 100 101 110 111 Bit 2-0 IRQ resource reflect other IRQ resources selected by PnP register (default) IRQ7 IRQ9 IRQ10 IRQ11 IRQ14 IRQ15 IRQ5 These five bits are at high level during a read and can be written. 5.3.10 ecr (Extended Control Register) Mode = all This register controls the extended ECP parallel port functions. The bit definitions are follows: 7 6 5 4 3 2 1 0 empty full service Intr dmaEn nErrIntrEn MODE MODE MODE Bit 7-5: These bits are read/write and select the mode. 000 001 Standard Parallel Port mode. The FIFO is reset in this mode. PS/2 Parallel Port mode. This is the same as 000 except that direction may be used to tri-state the data lines and reading the data register returns the value on the data lines and not the value in the data register. Parallel Port FIFO mode. This is the same as 000 except that bytes are written or DMAed to the FIFO. FIFO data are automatically transmitted using the standard parallel port protocol. This mode is useful only when direction is 0. ECP Parallel Port Mode. When the direction is 0 (forward direction), bytes placed into the ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and auto transmitted to the peripheral using ECP Protocol. When the direction is 1 (reverse direction), bytes are moved from the ECP parallel port and packed into bytes in the ecpDFifo. Selects EPP Mode. In this mode, EPP is activated if the EPP mode is selected. Reserved. Test Mode. The FIFO may be written and read in this mode, but the data will not be transmitted on the parallel port. Publication Release Date: April 2001 Revision 0.51 010 011 100 101 110 - 72 - W83697SF PRELIMINARY 111 Configuration Mode. The confgA and confgB registers are accessible at 0x400 and 0x401 in this mode. Bit 4: Read/Write (Valid only in ECP Mode) 1 Disables the interrupt generated on the asserting edge of nFault. 0 Enables an interrupt pulse on the high to low edge of nFault. If nFault is asserted (interrupt) an interrupt will be generated and this bit is written from a 1 to 0. Bit 3: Read/Write 1 Enables DMA. 0 Disables DMA unconditionally. Bit 2: Read/Write 1 Disables DMA and all of the service interrupts. 0 Enables one of the following cases of interrupts. When one of the service interrupts has occurred, the serviceIntr bit is set to a 1 by hardware. This bit must be reset to 0 to re-enable the interrupts. Writing a 1 to this bit will not cause an interrupt. (a) dmaEn = 1: During DMA this bit is set to a 1 when terminal count is reached. (b) dmaEn = 0 direction = 0: This bit is set to 1 whenever there are writeIntr Threshold or more bytes free in the FIFO. (c) dmaEn = 0 direction = 1: This bit is set to 1 whenever there are readIntr Threshold or more valid bytes to be read from the FIFO. Bit 1: Read only 0 The FIFO has at least 1 free byte. 1 The FIFO cannot accept another byte or the FIFO is completely full. Bit 0: Read only 0 The FIFO contains at least 1 byte of data. 1 The FIFO is completely empty. 5.3.11 Bit Map of ECP Port Registers D7 data ecpAFifo dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr PD7 Addr/RLE nBusy 1 ECP Data FIFO Test FIFO 0 compress 0 intrValue MODE 0 1 1 1 nErrIntrEn 0 1 dmaEn 0 1 serviceIntr 0 1 full 0 1 empty D6 PD6 nAck 1 D5 PD5 PError Directio D4 PD4 Select ackIntEn D3 PD3 nFault SelectIn D2 PD2 1 nInit D1 PD1 1 autofd D0 PD0 NOTE 2 Address or RLE field 1 strobe 1 1 2 2 2 Parallel Port Data FIFO - 73 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY Notes: 1. These registers are available in all modes. 2. All FIFOs use one common 16 -byte FIFO. - 74 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 5.3.12 ECP Pin Descriptions NAME nStrobe (HostClk) TYPE O DESCRIPTION The nStrobe registers data or address into the slave on the asserting edge during write operations. This signal handshakes with Busy. These signals contains address or data or RLE data. This signal indicates valid data driven by the peripheral when asserted. This signal handshakes with nAutoFd in reverse. This signal deasserts to indicate that the peripheral can accept data. It indicates whether the data lines contain ECP command information or data in the reverse direction. When in reverse direction, normal data are transferred when Busy (PeriphAck) is high and an 8-bit command is transferred when it is low. This signal is used to acknowledge a change in the direction of the transfer (asserted = forward). The peripheral drives this signal low to acknowledge nReverseRequest. The host relies upon nAckReverse to determine when it is permitted to drive the data bus. Indicates printer on line. Requests a byte of data from the peripheral when it is asserted. This signal indicates whether the data lines contain ECP address or data in the forward direction. When in forward direction, normal data are transferred when nAutoFd (HostAck) is high and an 8 -bit command is transferred when it is low. Generates an error interrupt when it is asserted. This signal is valid only in the forward direction. The peripheral is permitted (but not required) to drive this pin low to request a reverse transfer during ECP Mode. This signal sets the transfer direction (asserted = reverse, deasserted = forward). This pin is driven low to place the channel in the reverse direction. This signal is always deasserted in ECP mode. PD<7:0> nAck (PeriphClk) Busy (PeriphAck) I/O I I PError (nAckReverse) I Select (Xflag) nAutoFd (HostAck) I O nFault (nPeriphRequest) I nInit (nReverseRequest) O nSelectIn (ECPMode) O - 75 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 5.3.13 ECP Operation The host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol before ECP operation. After negotiation, it is necessary to initialize some of the port bits. The following are required: (a) Set direction = 0, enabling the drivers. (b) Set strobe = 0, causing the nStrobe signal to default to the deasserted state. (c) Set autoFd = 0, causing the nAutoFd signal to default to the deasserted state. (d) Set mode = 011 (ECP Mode) ECP address/RLE bytes or data bytes may be sent automatically by writing the ecpAFifo or ecpDFifo, respectively. Mode Switching Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ECP port only in the data transfer phase (mode 011 or 010). If the port is in mode 000 or 001 it may switch to any other mode. If the port is not in mode 000 or 001 it can only be switched into mode 000 or 001. The direction can be changed only in mode 001. When in extended forward mode, the software should wait for the FIFO to be empty before switching back to mode 000 or 001. In ECP reverse mode the software waits for all the data to be read from the FIFO before changing back to mode 000 or 001. Command/Data ECP mode allows the transfer of normal 8-bit data or 8 commands. In the forward direction, normal -bit data are transferred when HostAck is high and an 8-bit command is trans ferred when HostAck is low. The most significant bits of the command indicate whether it is a run-length count (for compression) or a channel address. In the reverse direction, normal data are transferred when PeriphAck is high and an 8-bit command is transferred when PeriphAck is low. The most significant bit of the command is always zero. Data Compression The W83627SF supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Note that the odd (RLE) compr ession in hardware is not supported. In order to transfer data in ECP mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo. 5.3.14 FIFO Operation The FIFO threshold is set in configuration register 5. All data transfers to or from the parallel port can proceed in DMA or Programmed I/O (non-DMA) mode, as indicated by the selected mode. The FIFO is used by selecting the Parallel Port FIFO mode or ECP Parallel Port Mode. After a reset, the FIFO is disabled. - 76 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 5.3.15 DMA Transfers DMA transfers are always to or from the ecpDFifo, tFifo, or CFifo. The DMA uses the standard PC DMA services. The ECP requests DMA transfers from the host by activating the PDRQ pin. The DMA will empty or fill the FIFO using the appropriate direction and mode. When the terminal count in the DMA controller is reached, an interrupt is generated and serviceIntr is asserted, which will disable the DMA. 5.3.16 Programmed I/O (NON-DMA) Mode The ECP or parallel port FIFOs can also be operated using interrupt driven programmed I/O. Programmed I/O transfers are to the ecpDFifo at 400H and ecpAFifo at 000H or from the ecpDFifo located at 400H, or to/from the tFifo at 400H. The host must set the direction, state, dmaEn = 0 and serviceIntr = 0 in the programmed I/O transfers. The ECP requests programmed I/O transfers from the host by activating the IRQ pin. The programmed I/O will empty or fill the FIFO using the appropriate direction and mode. 5.4 Extension FDD Mode (EXTFDD) In this mode, the W83627SF changes the printer interface pins to FDC input/output pins, allowing the user to install a second floppy disk drive (FDD B) through the DB-25 printer connector. The pin assignments for the FDC input/output pins are shown in Table 6-1. After the printer interface is set to EXTFDD mode, the following occur: (1) Pins MOB# and DSB# will be forced to inactive state. (2) Pins DSKCHG# , RDATA#, WP# , TRAK0#, INDEX# will be logically ORed with pins PD4-PD0 to serve as input signals to the FDC. (3) Pins PD4-PD0 each will have an internal resistor of about 1K ohm to serve as pull-up resistor for FDD open drain/collector output. (4) If the parallel port is set to EXTFDD mode after the system has booted DOS or another operating system, a warm reset is needed to enable the system to recognize the extension floppy drive. 5.5 Extension 2FDD Mode (EXT2FDD) In this mode, the W83627SF changes the printer interface pins to FDC input/output pins, allowing the user to install two external floppy disk drives through the DB-25 printer connector to replace internal floppy disk drives A and B. The pin assignments for the FDC input/output pins are shown in Table6-1. After the printer interface is set to EXTFDD mode, the following occur: (1) Pins MOA#, DSA#, MOB#, and DSB# will be forced to inactive state. (2) Pins DSKCHG# , RDATA#, WP#, TRAK0#, and INDEX# will be logically ORed with pins PD4-PD0 to serve as input signals to the FDC. (3) Pins PD4-PD0 each will have an internal resistor of about 1K ohm to serve as pull-up resistor for FDD open drain/collector output. (4) If the parallel port is set to EXT2FDD mode after the system has booted DOS or another operating system, a warm reset is needed to enable the system to recognize the extension floppy drive. - 77 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 6.0 GENERAL PURPOSE I/O W83697SF provides 60 input/output ports that can be individually configured to perform a simple basic I/O function or a pre-defined alternate function. Those 60 GP I/O ports are divided into three groups, each group contains 8 ports. The first gro up is configured through control registers in logical device 7, the second group in logical device 8, and the third group in logical device 9. Users can configure each individual port to be an input or output port by programming respective bit in selection register (CRF0: 0 = output, 1 = input). Invert port value by setting inversion register (CRF2: 0 = non -inverse, 1 = inverse). Port value is read/written through data register (CRF1). Table 7.1 and 7.2 gives more details on GPIO's assignment. In addition, GPIO1 is designed to be functional even in power loss condition (VCC or VSB is off). Figure 7.1 shows the GP I/O port's structure. Right after Power-on reset, those ports default to perform basic input function except ports in GPIO1 which maintains its previous settings until a battery loss condition. Table 7.1 SELECTION BIT 0 = OUTPUT 1 = INPUT 0 0 1 1 INVERSION BIT 0 = NON INVERSE 1 = INVERSE 0 1 0 1 Basic non-inverting output Basic inverting output Basic non-inverting input Basic inverting input BASIC I/O OPERATIONS - 78 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY Table 7.2 GP I/O PORT DATA REGISTER REGISTER BIT ASSIGNMENT BIT 0 BIT 1 BIT 2 BIT 3 GP1 BIT 4 BIT 5 BIT 6 BIT 7 BIT 0 BIT 1 GP2 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 0 BIT 1 BIT 2 BIT 3 GP3 BIT 4 BIT 5 BIT 6 BIT 7 GP I/O PORT GP10 GP11 GP12 GP13 GP14 GP15 GP16 GP17 GP20 GP21 GP22 GP23 GP24 GP25 GP26 GP27 GP30 GP31 GP32 GP33 GP34 GP35 GP36 GP37 - 79 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY Table 7.2, continued GP I/O PORT DATA REGISTER REGISTER BIT ASSIGNMENT BIT 0 BIT 1 BIT 2 BIT 3 GP I/O PORT GP40 GP41 GP42 GP43 GP44 GP45 GP46 GP47 GP50 GP51 GP52 GP53 GP54 GP55 GP56 GP57 GP60 GP61 GP62 GP63 GP64 GP65 GP66 GP67 GP4 BIT 4 BIT 5 BIT 6 BIT 7 BIT 0 BIT 1 BIT 2 GP5 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 0 BIT 1 BIT 2 BIT 3 GP6 BIT 4 BIT 5 BIT 6 BIT 7 - 80 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY Table 7.2, continued GP I/O PORT DATA REGISTER REGISTER BIT ASSIGNMENT BIT 0 BIT 1 BIT 2 GP I/O PORT GP70 GP71 GP72 GP73 GP74 GP75 GP76 GP77 GP80 GP81 GP82 GP83 GP7 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 0 GP8 BIT 1 BIT 2 BIT 3 Figure 7.1 - 81 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 7.0 ACPI REGISTERS FEATURES W83697SF supports both ACPI and legacy power managements. The switch logic of the power management block generates an SMI interrupt in the legacy mode and an PME interrupt in the ACPI mode. The new ACPI feature routes SMI / PME logic output either to SMI or to PME .The SMI / PME logic routes to SMI only when both PME_EN = 0 and SMIPME_OE = 1. Similarly, the SMI /PME logic routes to PME only when both PME_EN = 1 and SMIPME_OE = 1. PME_EN IRQ events SMIPME_OE SMI / PME Logic 0 1 SMIPME_OE SMI PME Device Idle Timers Device Trap Global STBY Timer IRQs Sleep/Wake State machine WAK_STS Clock Control - 82 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 8.0 PULSE WIDTH MODULATION (PWM) 8.1 General Description The W83697SF provides 3 sets for fan PWM speed control. The duty cycle of PWM can be programmed by the 8-bit registers which are defined in the CR01, CR03 and CR11. The default duty cycle is set to 100%, that is, the default 8-bit registers is set to FFh. the expression of duty can be represented as follows. Programmed 8 - bit Regist er Value + 1 x 100 % , 256 Programmed 8 - bit register v alue 0. Duty - cycle (%) = If programmed 8 - bit register v alue = 0, the duty cycle = 0 %. The PWM clock frequency also can be program and defined in the CR00, CR02 and CR10. The application circuit is shown as the Figure 9.1. +12V R1 R2 D G PWM Clock Input NMOS S PNP Transistor + - C FAN Figure 9.1 : The PWM application circuit 8.2 LPC Interface The interface uses LPC Bus to access which the ports of low byte (bit2~bit0) are defined in the port 5h and 6h. The other higher bits of these ports is set by W83697SF itself. The general decoded address is set to port 295h and port 296h. These two ports are described as following: Port 295h: Index port. Port 296h: Data port. - 83 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 8.3 REGISTERS 8.3.1 Address Register (Port x5h) Data Port: Power on Default Value Attribute: Size: Port x5h FFh Bit 7:0 Read/write 8 bits 7 6 5 4 3 2 1 0 Data Bit 7-0: Read/Write address pointer. 8.3.2 Data Register (Port x6h) Data Port: Power on Default Value Attribute: Size: Port x6h 00h Read/write 8 bits 7 6 5 4 3 2 1 0 Data Bit 7-0: Data to be read from or to be written to Register. - 84 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 8.3.3 PWM 1 Pre-Scale Re gister -- Index 00h Power on default [7:0] = 0000-0001 b Bit Name Read/Write Description 7 PWM_CLK_SEL1 Read/Write PWM 1 Input Clock Select. This bit select PWM 1 input clock to pre-scale divider. 0: 24 MHz 1: 187.5 KHz 6-0 PRE_SCALE1[6:0] Read/Write PWM 1 Input Clock Pre-Scale. The divider of input clock is the number defined by pre-scale. Thus, writing 0 transfers the input clock directly to counter. The maximum divider is 128 (7Fh). 00h : divider is 1 01h : divider is 2 02h : divider is 3 : : PWM 1 frequency = (Input Clock / Pre-scale) / 256 8.3.4 PWM 1 Duty Cycle Select Register - Index 01h Power on default [7:0] 1111,1111 b Bit Name Read/Write Description 7-0 PWM1_DC[7:0] Read/Write PWM 1 Duty Cycle. This 8-bit register determines the number of the 256-cycle period. 00h: PWM output is always logical Low. FFh: PWM output is always logical High. XXh: PWM output logical High percentage is (XX+1)/256*100% during one cycle. - 85 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 8.3.5 PWM 2 Pre-Scale Register -- Index 02h Power on default [7:0] = 0000,0001 b Bit Name Read/Write Description 7 PWM_CLK_SEL2 Read/Write PWM 2 Input Clock Select. This bit select PWM 2 input clock to pre-scale divider. 0: 24 MHz 1: 187.5 KHz 6-0 PRE_SCALE2[6:0] Read/Write PWM 2 Input Clock Pre-Scale. The divider of input clock is the number defined by pre-scale. Thus, writing 0 transfers the input clock directly to counter. The maximum divider is 128 (7Fh). 00h : divider is 1 01h : divider is 2 02h : divider is 3 : : PWM 2 frequency = (Input Clock / Pre-scale) / 256 8.3.6 PWM 2 Duty Cycle Select Register -- Index 03h Power on default [7:0] = 1111,1111 b Bit Name Read/Write Description 7-0 PWM2_DC[7:0] Read/Write PWM 2 Duty Cycle. This 8-bit register determines the number of the 256-cycle period. 00h: PWM output is always logical Low. FFh: PWM output is always logical High. XXh: PWM output logical High percentage is (XX+1)/256*100% during one cycle. - 86 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 8.3.7 PWM 0 Pre-Scale Register -- Index 10h Power on default [7:0] = 0000-0001 b Bit Name Read/Write Description 7 PWM_CLK_SEL0 Read/Write PWM 0 Input Clock Select. This bit select PWM 0 input clock to pre-scale divider. 0: 24 MHz 1: 187.5 KHz 6-0 PRE_SCALE0[6:0] Read/Write PWM 0 Input Clock Pre-Scale. The divider of input clock is the number defined by pre-scale. Thus, writing 0 transfers the input clock directly to counter. The maximum divider is 128 (7Fh). 00h : divider is 1 01h : divider is 2 02h : divider is 3 : : PWM 0 frequency = (Input Clock / Pre-scale) / 256 8.3.8 PWM 0 Duty Cycle Select Register - Index 11h Power on default [7:0] 1111,1111 b Bit Name Read/Write Description 7-0 PWM0_DC[7:0] Read/Write PWM 0 Duty Cycle. This 8 register determines the -bit number of the 256-cycle period. 00h: PWM output is always logical Low. FFh: PWM output is always logical High. XXh: PWM output logical High percentage is (XX+1)/256*100% during one cycle. - 87 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 9.0 CONFIGURATION REGISTER 9.1 Plug and Play Configuration The W83697SF uses Compatible PNP pro tocol to access configuration registers for setting up different types of configurations. In W83697SF, there are eleven Logical Devices (from Logical Device 0 to Logical Device B with the exception of logical device 4 for backward compatibility) which correspond to eleven individual functions: FDC (logical device 0), PRT (logical device 1), UART1 (logical device 2), UART2 (logical device 3), CIR (Consumer IR, logical device 6), GPIO1 (logical device 7), GPIO5(logical device 8),GPIO2 ~GPIO4(logical device 9), ACPI ((logical device A), and Hardware monitor (logical device B). Each Logical Device has its own configuration registers (above CR30). Host can access those registers by writing an appropriate logical device number into logical device select register at CR7. 7 x 6 x 5 x 4 x 3 x 2 x 1 0 DRATE0 DRATE1 9.2 Compatible PnP 9.2.1 Extended Function Registers In Compatible PnP, there are two ways to enter Extended Function and read or write the configuration registers. HEFRAS (CR26 bit 6) can be used to select one out of these two methods of entering the Extended Function mode as follows: HEFRAS 0 1 address and value write 87h to the location 2Eh twice write 87h to the location 4Eh twice After Power-on reset, the value on RTSA# (pin 49) is latched by HEFRAS of CR26. In Compatible PnP, a specific value (87h) must be written twice to the Extended Functions Enable Register (I/O port address 2Eh or 4Eh). Secondly, an index value (02h, 07h -FFh) must be written to the Extended Functions Index Register (I/O port address 2Eh or 4Eh same as Extended Functions Enable Register) to identify which configuration register is to be accessed. The designer can then access the desired configuration register through the Extended Functions Data Register (I/O port address 2Fh or 4Fh). After programming of the c onfiguration register is finished, an additional value (AAh) should be written to EFERs to exit the Extended Function mode to prevent unintentional access to those configuration registers. The designer can also set bit 5 of CR26 (LOCKREG) to high to protect the configuration registers against accidental accesses. Publication Release Date: April 2001 Revision 0.51 - 88 - W83697SF PRELIMINARY The configuration registers can be reset to their default or hardware settings only by a cold reset (pin MR = 1). A warm reset will not affect the configuration registers. 9.2.2 Extended Functions Enable Registers (EFERs) After a power-on reset, the W83697SF enters the default operating mode. Before the W83697SF enters the extended function mode, a specific value must be programmed into the Extended Function Enable Register (EFER) so that the extended function register can be accessed. The Extended Function Enable Registers are write-only registers. On a PC/AT system, their port addresses are 2Eh or 4Eh (as described in previous section). 9.2.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs) After the extended function mode is entered, the Extended Function Index Register (EFIR) must be loaded with an index value (02h, 07h-FEh) to access Configuration Register 0 (CR0), Configuration Register 7 (CR07) to Con figuration Register FE (CRFE), and so forth through the Extended Function Data Register (EFDR). The EFIRs are write-only registers with port address 2Eh or 4Eh (as described in section 12.2.1) on PC/AT systems; the EFDRs are read/write registers with port address 2Fh or 4Fh (as described in section 9.2.1) on PC/AT systems. 9.3 Configuration Sequence To program W83697SF configuration registers, the following configuration sequence must be followed: (1). Enter the extended function mode (2). Configure the configuration registers (3). Exit the extended function mode 9.3.1 Enter the extended function mode To place the chip into the extended function mode, two successive wrtites of 0x87 must be applied to Extended Function Enable Registers(EFERs, i.e. 2Eh or 4Eh). 9.3.2 Configurate the configuration registers The chip selects the logical device and activates the desired logical devices through Extended Function Index Register(EFIR) and Extended Function Data Register(EFDR). EFIR is located at the same address as EFER, and EFDR is located at address (EFIR+1). First, write the Logical Device Number (i.e.,0x07) to the EFIR and then write the number of the desired logical device to the EFDR. If accessing the Chip(Global) Control Registers, this step is not required. Secondly, write the address of the desired configuration register within the logical device to the EFIR and then write (or read) the desired configuration register through EFDR. 9.3.3 Exit the extended function mode To exit the extended function mode, one write of 0xAA to EFER is required. Once the chip exits the extended function mode, it is in the normal running mode and is ready to enter the configuration mode. Publication Release Date: April 2001 Revision 0.51 - 89 - W83697SF PRELIMINARY 9.3.4 Software programming example The following example is written in Intel 8086 assembly language. It assumes that the EFER is located at 2Eh, so EFIR is located at 2Eh and EFDR is located at 2Fh. If HEFRAS (CR26 bit 6) is set, 4Eh can be directly replaced by 4Eh and 2Fh replaced by 4Fh. ;---------------------------------------------- ------------------------------------; Enter the extended function mode ,interruptible double-write ;----------------------------------------------------------------------------------MOV OUT OUT DX,2EH DX,AL DX,AL MOV AL,87H | ;----------------------------------------------------------------------------; Configurate logical device 1, configuration register CRF0 | ;----------------------------------------------------------------------------MOV MOV OUT MOV MOV OUT ; MOV MOV OUT MOV OUT DX,2EH AL,F0H DX,AL DX,2FH DX,AL ; update CRF0 with value 3CH | ; select CRF0 DX,2EH AL,07H DX,AL DX,2FH AL,01H DX,AL ; select logical device 1 ; point to Logical Devi ce Number Reg. MOV AL,3CH ;-----------------------------------------; Exit extended function mode ;-----------------------------------------MOV OUT DX,2EH DX,AL MOV AL,AAH - 90 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 9.4 Chip (Global) Control Register CR02 (Default 0x00) (Write only) Bit [7:1]: Bit 0 CR07 Bit [7:0]: LDNB7 - LDNB0 --> Logical Device Number Bit 7 - 0 CR20 (read only) Bit [7:0]: DEVIDB7 - DEBIDB0 --> Device ID Bit 7 - Bit 0 = 0x 68 (for W83697SF & W83697SF) = 0x 60 (for W83697F) CR21 (read only) Bit [7:0]: DEVREVB7 - DEBREVB0 --> Device Rev = 0x1X (for W83697SF) = 0x0X (for W83697SF) = 0x1Y (for W83697F) X : Version change number. (Bit [3:0]) --> begin from 1 Y : Version change number. (Bit [3:0]) --> begin from F CR22 (Default 0xef) Bit 7: SCPWD 0 1 Bit 6: 0 1 Bit 5: 0 1 Power down No Power down Power down No Power down Power down No Power down Reserved. = 1 SWRST --> Soft Reset. URDPWD URCPWD - 91 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY Bit 4: Bit 3: Reserved URBPWD 0 1 Bit 2: 0 1 Bit 1: 0 1 Bit 0: 0 1 CR23 (Default 0xfe) Bit [7:1]: Reserved. Bit 0: IPD (Immediate Power Down). When set to 1, it will put the whole chip into power down mode immediately. CR24 (Default 0s1000ss) Bit 7: Flash ROM I/F Address Segment (000F0000h ~ 000FFFFFh) enable/disable 0 1 Bit 6: 0 1 Enable Disable The clock input on Pin 1 should be 24 MHz. The clock input on Pin 1 should be 48 MHz. The corresponding power-on setting pin is SOUTB (pin 61). Bit [5:4]: ROM size select 00 01 10 11 Bit 3: 0 1M 2M 4M Reserved MEMW# Disable Power down No Power down Power down No Power down Power down No Power down Power down No Power down URAPWD PRTPWD FDCPWD CLKSEL(Enable 48Mhz) MEMW# Select (PIN97) - 92 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 1 MEMW# Enable - 93 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY Bit 2: Flash ROM I/F Address Segment (000E0000h ~ 000EFFFFh) enable/disable 0 1 Enable Disable Flash ROM Interface is enabled after hardware reset Flash ROM Interface is disabled after hardware reset The corresponding power-on setting pin is PENROM#(pin 52) Bit 1 : Enable Flash ROM Interface 0 1 Bit 0: PNPCSV 0 1 The Compatible PnP address select registers have default values. The Compatible PnP address select registers have no default value. The corresponding power-on setting pin is DTRA# (pin 50). CR25 (Default 0x00) Bit 7: Bit 6: Bit 5: Bit 4: Bit 3: Bit 2: Bit 1: Bit 0: SCTRI URDTRI URCTRI Reserved URBTRI URATRI PRTTRI FDCTRI CR26 (Default 0x00) Bit 7: SEL4FDD 0 1 Bit 6: Select two FDD mode. Select four FDD mode. HEFRAS These two bits define how to enable Configuration mode. The corresponding power-on setting pin is RTSA #(pin 49). HEFRAS Address and Value 0 1 Write 87h to the location 2E twice. Write 87h to the location 4E twice. - 94 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY Bit 5: LOCKREG 0 1 Enable R/W Configuration Registers. Disable R/W Configuration Registers. Bit 4: Bit 3: Reserved DSFDLGRQ 0 1 Enable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is effective on selecting IRQ Disable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is not effective on selecting IRQ Enable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is effective on selecting IRQ Disable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is not effective on selecting IRQ Enable UART A/C legacy mode IRQ selecting, then HCR bit 3 is effective on selecting IRQ Disable UART A/C legacy mode IRQ selecting, then HCR bit 3 is not effective on selecting IRQ Enable UART B/D legacy mode IRQ selecting, then HCR bit 3 is effective on selecting IRQ Disable UART B/D legacy mode IRQ selecting, then HCR bit 3 is not effective on selecting IRQ Bit 2: DSPRLGRQ 0 1 Bit 1: DSUALGRQ 0 1 Bit 0: DSUBLGRQ 0 1 CR28 (Default 0x00) Bit [7:4]: Reserved. Bit [3]: Flash ROM I/F Address Segment (FFE80000h ~ FFEFFFFFh) enable/disable 0 1 0xx 100 101 110 Disable Enable Parallel Port Mode Reserved External FDC Mode Reserved Bit [2:0]: PRTMODS2 - PRTMODS0 - 95 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 111 External two FDC Mode CR29 (GPIO1,5(50~51) & Game port & MIDI port Select. Default 0x00 ) Bit 7: Port Select (select Game Port or General Purpose I/O Port 1) 0 1 00 01 10 11 00 01 10 11 Bit 2: Game Port General Purpose I/O Port 1 (pin121~128 select function GP10~GP17) MSI Reserved Reserved GP51 MSO Reserved Reserved GP50 Bit [6:5]: (Pin119) Bit [4:3]: (Pin 120) (Pin117) OVT# & SMI Select(Pin117) 0 1 OVT# SMI# Bit [1:0]: Reserved CR2A(GPIO2 ~ 5& Fresh ROM Interface Select, default 0xFF if PENROM# = 0 during POR, default 0x00 otherwise) Bit 7: (PIN 86 ~89 & 91 ~94) 0 1 Bit 6: 0 1 Bit 5: 0 1 GPIO 2 Fresh IF (xD7 ~ XD0) GPIO 3 Fresh IF (XA7 ~ XA0) GPIO 4 Fresh IF (XA15 ~ XA10 & XA9 ~ A8) (PIN 78 ~ 85) (PIN 69 ~ 74 & 76 ~77) - 96 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY - 97 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY Bit 4: (PIN 66 ~ 68 & 95 ~ 97) 0 1 GPIO 5(GP52 ~ 57) Fresh IF(XA18 ~ XA16 , ROMCS#, MEMR #, MEMW#) Bit [3:0]: Reserved CR2B(PWM & GPIO8, URC & GPIO6 Select. Default 0x00 (for W83697SF & W83697F) Default 0x03 (for W83697SF)) Bit [7]: Reserved. 00 01 10 11 Bit [4]: 0 1 Bit [3]: 0 1 Bit [2]: 0 1 Bit [1]: 0 1 Bit [0]: 0 1 PWM2 PLED Reserved GP83 PWM1 GP82 PWM0 GP81 WDTO GP80 URC(NCTSC, NDSRC, NRTSC, NDTRC, NDCDC, NRIC) GPIO6(GP67, GP66, GP65, GP64, GP61, GP60) URC(SINC, SOUTC) GPIO6(GP63, GP62) Bit [6:5]: (Pin115) (Pin116) (Pin117) (Pin118) (Pin99, Pin100, Pin101, Pin102, Pin105, Pin106) (Pin103, Pin104) - 98 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY CR2C(SC & URD & GPIO7 Select. Default 0x30 (for W83697SF & W83697SF & W83697F) Bit [7:6]: (Pin107, Pin108, Pin109, Pin110, Pin113) 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 SC(SCPSNT, SCIO,SCCLK, SCRST, SCPWR) URD(NCTSD,NDSRD, NRTSD, NDTRD, NDCDD) Reserved GPIO7(GP77, GP76, GP75, GP74, GP71) Reserved SIND Reserved GP73 SCC8 SOUTD Reserved GP72 SCC4 NRID Reserved GP70 Bit [5:4]: (Pin111) Bit [3:2]: (Pin112) Bit [1:0]: (Pin114) 9.5 Logical Device 0 (FDC) CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit [7:1]: Reserved. Bit 0: 1 0 Activates the logical device. Logical device is inactive. CR60, CR61 (Default 0x03, 0xf0 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select FDC I/O base address [0x100:0xFF8] on 8 byte boundary. - 99 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY CR70 (Default 0x06 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit [7:4]: Reserved. Bit [3:0]: These bits select IRQ resource for FDC. CR74 (Default 0x02 if PNPCSV = 0 during POR, default 0x04 otherwise) Bit [7:3]: Reserved. Bit [2:0]: These bits select DRQ resource for FDC. = 0x00 DMA0 = 0x01 DMA1 = 0x02 DMA2 = 0x03 DMA3 = 0x04 - 0x07 No DMA active CRF0 (Default 0x0E) FDD Mode Register Bit 7: FIPURDWN This bit controls the internal pull-up resistors of the FDC input pins RDATA, INDEX, TRAK0, DSKCHG, and WP. 0 1 Bit 6: The internal pull-up resistors of FDC are turned on.(Default) The internal pull-up resistors of FDC are turned off. INTVERTZ This bit determines the polarity of all FDD interface signals. 0 1 FDD interface signals are active low. FDD interface signals are active high. Bit 5: DRV2EN (PS2 mode only) When this bit is a logic 0, indicates a second drive is installed and is reflected in status register A. Bit 4: Swap Drive 0, 1 Mode 0 1 11 10 01 00 No Swap (Default) Drive and Motor select 0 and 1 are swapped. AT Mode (Default) (Reserved) PS/2 Model 30 Publication Release Date: April 2001 Revision 0.51 Bit 3 - 2 Interface Mode - 100 - W83697SF PRELIMINARY Bit 1: FDC DMA Mode 0 1 Bit 0 0 1 CRF1 (Default 0x00) Bit 7 - 6 Boot Floppy 00 01 10 11 FDD A FDD B FDD C FDD D Burst Mode is enabled Non-Burst Mode (Default) Normal Floppy Mode (Default) Enhanced 3-mode FDD Floppy Mode Bit [5:4]: Media ID1, Media ID0. These bits will be reflected on FDC's Tape Drive Register bit 7, 6. Bit [3:2]: Density Select 00 01 10 11 Bit 1: 0 1 Bit 0: 0 1 Normal (Default) Normal 1 ( Forced to logic 1) 0 ( Forced to logic 0) Enable FDD write. Disable FDD write(forces pins WE, WD stay high). Normal, use WP to determine whether the FDD is write protected or not. FDD is always write-protected. DISFDDWR SWWP CRF2 (Default 0xFF) Bit [7:6]: FDD D Drive Type Bit [5:4]: FDD C Drive Type Bit [3:2]: FDD B Drive Type Bit [1:0]: FDD A Drive Type - 101 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY CRF4 (Default 0x00) FDD0 Selection: Bit 7: Bit 6: Reserved. Precomp. Disable. 1 0 Bit 5: Disable FDC Precompensation. Enable FDC Precompensation. Reserved. 00 01 10 11 Select Regular drives and 2.88 format 3-mode drive 2 Meg Tape Reserved Bit 4 - 3: DRTS1, DRTS0: Data Rate Table select (Refer to TABLE A). Bit 2: Reserved. Bit [1:0]: DTYPE0, DTYPE1: Drive Type select (Refer to TABLE B). CRF5 (Default 0x00) FDD1 Selection: Same as FDD0 of CRF4. TABLE A Drive Rate Table Select DRTS1 DRTS0 0 0 Data Rate DRATE1 1 0 0 1 1 0 0 1 1 0 0 1 DRATE0 1 0 1 0 1 0 1 0 1 0 1 0 Selected Data Rate MFM 1Meg 500K 300K 250K 1Meg 500K 500K 250K 1Meg 500K 2Meg 250K FM --250K 150K 125K --250K 250K 125K --250K --125K SELDEN 0 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 - 102 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY TABLE B DTYPE0 0 DTYPE1 0 DRVDEN0(pin 2) SELDEN DRVDEN1(pin 3) DRATE0 DRIVE TYPE 4/2/1 MB 3.5"" 2/1 MB 5.25" 2/1.6/1 MB 3.5" (3-MODE) 0 1 1 1 0 1 DRATE1 SELDEN DRATE0 DRATE0 DRATE0 DRATE1 9.6 Logical Device 1 (Parallel Port) CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit [7:1]: Reserved. Bit 0: 1 0 Activates the logical device. Logical device is inactive. CR60, CR61 (Default 0x03, 0x78 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select Parallel Port I/O base address. [0x100:0xFFC] on 4 byte boundary (EPP not supported) or [0x100:0xFF8] on 8 byte boundary (all modes supported, EPP is only available when the base address is on 8 byte boundary). CR70 (Default 0x07 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit [7:4]: Reserved. Bit [3:0]: These bits select IRQ resource for Parallel Port. - 103 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY CR74 (Default 0x03) Bit [7:3]: Reserved. Bit [2:0]: These bits select DRQ resource for Parallel Port. 0x00=DMA0 0x01=DMA1 0x02=DMA2 0x03=DMA3 0x04 - 0x07= No DMA active CRF0 (Default 0x3F) Bit 7: Reserved. Bit [6:3]: ECP FIFO Threshold. Bit [2:0]: Parallel Port Mode (CR28 PRTMODS2 = 0) 100 000 001 101 010 011 111 Printer Mode Standard and Bi-direction (SPP) mode EPP - 1.9 and SPP mode EPP - 1.7 and SPP mode ECP mode ECP and EPP - 1.9 mode ECP and EPP - 1.7 mode (Default) 9.7 Logical Device 2 (UART A) CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit [7:1]: Reserved. Bit 0: 1 0 Activates the logical device. Logical device is inactive. CR60, CR61 (Default 0x03, 0xF8 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select Serial Port 1 I/O base address [0x100:0xFF8] on 8 byte boundary. CR70 (Default 0x04 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit [7:4]: Reserved. - 104 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY Bit [3:0]: These bits select IRQ resource for Serial Port 1. CRF0 (Default 0x00) Bit 7: Bit 6: Reserved. 1 0 Activates the logical device IRQ sharing function. Logical device IRQ sharing is inactive. Bit [5:2]: Reserved. Bit [1:0]: SUACLKB1, SUACLKB0 00 01 10 11 UART A clock source is 1.8462 Mhz (24MHz/13) UART A clock source is 2 Mhz (24MHz/12) UART A clock source is 24 Mhz (24MHz/1) UART A clock source is 14.769 Mhz (24mhz/1.625) 9.8 Logical Device 3 (UART B) CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit [7:1]: Reserved. Bit 0: 1 0 Activates the logical device. Logical device is inactive. CR60, CR61 (Default 0x02, 0xF8 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select Serial Port 2 I/O base address [0x100:0xFF8] on 8 byte boundary. CR70 (Default 0x03 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit [7:4]: Reserved. Bit [3:0]: These bits select IRQ resource for Serial Port 2. CRF0 (De fault 0x00) Bit 7: Bit 6: Reserved. 1 0 Activates the logical device IRQ sharing function. Logical device IRQ sharing is inactive. Bit [5:4]: Reserved. - 105 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY Bit 3: RXW4C 0 1 No reception delay when SIR is changed from TX mode to RX mode. Reception delays 4 characters-time (40 bit-time) when SIR is changed from TX mode to RX mode. No transmission delay when SIR is changed from RX mode to TX mode. Transmission delays 4 characters-time (40 bit-time) when SIR is changed from RX mode to TX mode. UART B clock source is 1.8462 Mhz (24MHz/13) UART B clock source is 2 Mhz (24MHz/12) UART B clock source is 24 Mhz (24MHz/1) UART B clock source is 14.769 Mhz (24mhz/1.625) Bit 2: TXW4C 0 1 Bit [1:0]: SUBCLKB1, SUBCLKB0 00 01 10 11 CRF1 (Default 0x00) Bit 7: Bit 6: Reserved. IRLOCSEL. IR I/O pins' location select. 0 1 Bit 5: Bit 4: Bit 3: Through SINB/SOUTB. Through IRRX/IRTX. IRMODE2. IR function mode selection bit 2. IRMODE1. IR function mode selection bit 1. IRMODE0. IR function mode selection bit 0. IR MODE 00X 010* 011* 100 101 110 111* IR FUNCTION Disable IrDA IrDA ASK-IR ASK-IR ASK-IR ASK-IR tri-state IRTX high Active pulse 1.6 S Active pulse 3/16 bit time Inverting IRTX/S OUTB pin Inverting IRTX/SOUTB & 500 KHZ clock Inverting IRTX/SOUTB Inverting IRTX/SOUTB & 500 KHZ clock IRRX Demodulation into SINB/IRRX Demodulation into SINB/IRRX routed to SINB/IRRX routed to SINB/IRRX Demodulation into SINB/IRRX Demodulation into SINB/IRRX Note: The notation is normal mode in the IR function. - 106 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY Bit 2: HDUPLX. IR half/full duplex function select. 0 1 Bit 1: 0 1 Bit 0: 0 1 The IR function is Full Duplex. The IR function is Half Duplex. the SOUTB pin of UART B function or IRTX pin of IR function in normal condition. inverse the SOUTB pin of UART B function or IRTX pin of IR function. the SINB pin of UART B function or IRRX pin of IR function in normal condition. inverse the SINB pin of UART B function or IRRX pin of IR function TX2INV. RX2INV. 9.9 Logical Device 7 (Game Port and GPIO Port 1) CR30 (Default 0x00) Bit [7:1]: Reserved. Bit 0: 1 0 Game/GP1 Port is active. Game/GP1 Port is inactive. CR60, CR61 (Default 0x02, 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) These two registers select the Game Port base address [0x100:0xFFF] on 8 byte boundary. CR62, CR63 (Default 0x00, 0x00) These two registers select the GPIO1 base address [0x100:0xFFF] on 1 byte boundary IO address : CRF1 base address CRF0 (GP10-GP17 I/O selection register. Default 0xFF) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF1 (GP10-GP17 data register. Default 0x00) If a port is programmed to be an output port, then its respective bit can be read/written If a port is programmed to be an input port, then its respective bit can only be read. CRF2 (GP10-GP17 inversion register. Default 0x00) When set to a '1', the incoming/outgoing port value is inverted. Publication Release Date: April 2001 Revision 0.51 - 107 - W83697SF PRELIMINARY When set to a '0', the incoming/outgoing port value is the same as in data register. 9.10 Logical Device 8 (MIDI Port and GPIO Port 5) CR30 (MIDI Port Default 0x00) Bit [7:1]: Reserved. Bit 0: 1 0 MIDI/GP5 port is activate MIDI/GP5 port is inactive. CR60, CR61 (Default 0x03, 0x30 if PNPCSV = 0 during POR, default 0x00 otherwise) These two registers select the MIDI Port base address [0x100:0xFFF] on 2byte boundary. CR62, CR63 (Default 0x00, 0x00 ) These two registers select the GPIO5 base address [0x100:0xFFF] on 4byte boundary. IO address : CRF1 base address IO address + 1 : CRF3 base address IO address + 2 : CRF4 base address IO address + 3 : CRF5 base address CR70 (Default 0x09 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit [7:4]: Reserved. Bit [3:0]: These bits select IRQ resource for MIDI Port . CRF0 (GP5 selection register. Default 0xFF) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF1 (GP5 data register. Default 0x00) If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF2 (GP 5 inversion register. Default 0x00) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. Publication Release Date: April 2001 Revision 0.51 - 108 - W83697SF PRELIMINARY CRF3 (PLED mode register. Default 0x00) Bit [7:3] : Bit 2: Reserved . select WDTO count mode. 0 1 00 01 10 11 CRF4 (Default 0x00) Watch Dog Timer Time-out value. Writing a non-zero value to this register causes the counter to load the value to Watch Dog Counter and start counting down. Reading this register returns current value in Watch Dog Counter instead of Watch Dog Timer Time-out value. Bit [7:0]: = 0x00 Time-out Disable = 0x01 Time-out occurs after 1 second/minute = 0x02 Time-out occurs after 2 second/minutes = 0x03 Time-out occurs after 3 second/minutes ................................................ = 0xFF Time-out occurs after 255 second/minutes CRF5 (Default 0x00) Bit [7] : Bit [6] : Bit 5: Bit 4: Reserved . invert Watch Dog Timer Status Force Watch Dog Timer Time-out, Write only* 1 1 0 Force Watch Dog Timer time-out event; this bit is self-clearing. Watch Dog Timer time-out occurred. Watch Dog Timer counting Watch Dog Timer Status, R/W second minute Power LED pin is tri-stated. Power LED pin is droved low. Power LED pin is a 1Hz toggle pulse with 50 duty cycle. Power LED pin is a 1/4Hz toggle pulse with 50 duty cycle. Bit [1:0]: select PLED mode Bit [3:0]: These bits select IRQ resource for Watch Dog. Setting of 2 selects SMI. - 109 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 9.11 Logical Device 9 (GPIO Port 2 ~ GPIO Port 4 ) CR30 (Default 0x00) Bit [7:3]: Reserved. Bit 2: Bit 1: Bit 0: 1 0 1 0 1 0 GP4 port is active. GP4 port is inactive GP3 port is active. GP3 port is inactive GP2 port is active. GP2 port is inactive. CR60,CR61(Default 0x00,0x00). These two registers select the GP2,3,4 base address(0x100:FFF) ON 3 bytes boundary. IO address: CRF1 base address IO address + 1 : CRF4 base address IO address + 2 : CRF7 base address CRF0 (GP2 I/O selection register. Default 0xFF ) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF1 (GP2 data register. Default 0x00 ) If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF2 (GP2 inversion register. Default 0x00 ) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. CRF3 (GP3 I/O selection register. Default 0xFF ) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF4 (GP3 data register. Default 0x00 ) If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. Publication Release Date: April 2001 Revision 0.51 - 110 - W83697SF PRELIMINARY CRF5 (GP3 inversion register. Default 0x00 ) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. CRF6 (GP4 I/O selection register. Default 0xFF ) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF7 (GP4 data register. Default 0x00 ) If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF8 (GP4 inversion register. Default 0x00 ) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. 9.12 Logical Device A (ACPI) CR30 (Default 0x00) Bit [7:1]: Reserved. Bit 0: 1 0 CR70 (Default 0x00) Bit [7:4]: Reserved. Bit [3:0]: These bits select IRQ resources for SMI PME / CRF0 (Default 0x00) Bit 7: CHIPPME. Chip level auto power management enable. 0 1 Bit 6: disable the auto power management functions enable the auto power management functions. Activates the logical device. Logical device is inactive. Reserved. (Return zero when read) - 111 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY - 112 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY Bit 5: MIDIPME. MIDI port auto power management enable. 0 1 disable the auto power management functions enable the auto power management functions Bit 4: Bit 3: Reserved. (Return zero when read) PRTPME. PRT auto power management enable. 0 1 disable the auto power management functions. enable the auto power management functions. disable the auto power management functions. enable the auto power management functions. disable the auto power management functions. enable the auto power management functions. disable the auto power management functions. enable the auto power management functions. Bit 2: FDCPME. FDC auto power management enable. 0 1 Bit 1: URAPME. UART A auto power management enable. 0 1 Bit 0: URBPME. UART B auto power management enable. 0 1 CRF1 (Default 0x00) Bit 7: WAK_STS. This bit is set when the chip is in the sleeping state and an enabled resume event occurs. Upon setting this bit, the sleeping/working state machine will transition the system to the working state. This bit is only set by hardware and is cleared by writing a 1 to this bit position or by the sleeping/working state machine automatically when the global standby timer expires. 0 1 Bit 6: Bit 5: Bit 4: Bit 3: Bit 2: Bit 1: Bit 0: the chip is in the sleeping state. the chip is in the working state. Reserved. (Return zero when read) MIDI's trap status. Reserved. (Return zero when read) PRT's trap status. FDC's trap status. URA's trap status. URB's trap status. - 113 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY CRF2 (Default 0x00) Bit [7:3]: Reserved. (Return zero when read) Bit 2: Bit 1: Bit 0: SC's trap status. URD's trap status. URC's trap status. CRF3 (Default 0x00) These bits indicate the IRQ status of the individual device respectively. The device's IRQ status bit is set by their source device and is cleared by writing a 1. Writing a 0 has no effect. Bit 7: Bit 6: Bit 3: Bit 2: Bit 1: Bit 0: URDIRQSTS. URD IRQ status. URCIRQSTS. URC IRQ status. PRTIRQSTS. PRT IRQ status. FDCIRQSTS. FDC IRQ status. URAIRQSTS. UART A IRQ status. URBIRQSTS. UART B IRQ status. Bit [5:4]: Reserved. (Return zero when read) CRF4 (Default 0x00) These bits indicate the IRQ status of the individual GPIO function or logical device respectively. The status bit is set by their source function or device and is cleared by writing a 1. Writing a 0 has no effect. Bit 7: Bit 6: Bit 2: Bit 1: Bit 0: Reserved. (Return zero when read) SCIRQSTS. SC IRQ status. WDTIRQSTS. Watch dog timer IRQ status. Reserved. (Return zero when read). MIDIIRQSTS. MIDI IRQ status. Bit [5:3]: Reserved. (Return zero when read) CRF6 (Default 0x00) These bits enable the generation of an SMI /PME interrupt due to any IRQ of the devices. SMI /PME logic output = (PRTIRQEN and PRTIRQSTS) or (FDCIRQEN and FDCIRQSTS) or (URAIRQEN and URAIRQSTS) or (URBIRQEN and URBIRQSTS) or (URCIRQEN and URCIRQSTS) or (WDTIRQEN and WDTIRQSTS) or (URDIRQEN and URDIRQEN) or (MIDIIRQEN and MIDIIRQEN) or (SCIRQEN and SCIRQEN) - 114 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY Bit 7: URDIRQEN. 0 1 Bit 6: disable the generation of an SMI / PME interrupt due to URD's IRQ. enable the generation of an SMI / PME interrupt due to URD's IRQ. URCIRQEN. 0 1 disable the generation of an SMI / PME interrupt due to URC's IRQ. enable the generation of an SMI / PME interrupt due to URC's IRQ. Bit [5:4]: Reserved (Return zero when read) Bit 3: PRTIRQEN. 0 1 Bit 2: disable the generation of an SMI / PME interrupt due to PRT's IRQ. enable the generation of an SMI / PME interrupt due to PRT's IRQ. FDCIRQEN. 0 1 disable the generation of an SMI / PME interrupt due to FDC's IRQ. enable the generation of an SMI / PME interrupt due to FDC's IRQ. Bit 1: URAIRQEN. 0 1 disable the generation of an SMI / PME interrupt due to UART A's IRQ. enable the generation of an SMI / PME interrupt due to UART A's IRQ. Bit 0: URBIRQEN. 0 1 disable the generation of an SMI / PME interrupt due to UART B's IRQ. enable the generation of an SMI / PME interrupt due to UART B's IRQ. CRF7 (Default 0x00) These bits enable the generation of an SMI /PME interrupt due to any IRQ of the devices. Bit 7: Bit 6: Reserved. (Return zero when read) SCIRQEN. 0 1 disable the generation of an SMI / PME interrupt due to SC timer's IRQ. enable the generation of an SMI / PME interrupt due to SC timer's IRQ. Bit [5:3]: Reserved. (Return zero when read) Bit 2: WDTIRQEN. 0 1 Bit 1: disable the generation of an SMI / PME interrupt due to watch dog timer's IRQ. enable the generation of an SMI / SMI interrupt due to watch dog timer's IRQ. Reserved. (Return zero when read) - 115 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY Bit 0: MIDIIRQEN. 0 1 disable the generation of an SMI / PME interrupt due to MIDI's IRQ. enable the generation of an SMI / PME interrupt due to MIDI's IRQ. CRF9 (Default 0x00) Bit [7:3]: Reserved. Return zero when read. Bit 2: PME_EN: Select the power management events to be either an PME or SMI interrupt for the IRQ events. Note that: this bit is valid only when SMIPME_OE = 1. 0 1 Bit 1: the power management events will generate an SMI event. the power management events will generate an PME event. 1S 8 mS FSLEEP: This bit selects the fast expiry time of individual devices. 0 1 Bit 0: SMIPME_OE: This is the SMI and PME output enable bit. 0 1 neither SMI nor PME will be generated. Only the IRQ status bit is set. an SMI or PME event will be generated. CRFA (Default 0x00) Bit [7:3]: Reserved. (Return zero when read) Bit 2: SCPME. SC auto power management enable. 0 1 Bit 1: 0 1 Bit 0: 0 1 disable the auto power management functions. enable the auto power management functions. disable the auto power management functions. enable the auto power management functions. disable the aut o power management functions. enable the auto power management functions. URDPME. UART D auto power management enable. URCPME. UART C auto power management enable. - 116 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 9.13 Logical Device B (PWM) CR30 (Default 0x00) Bit [7:1]: Reserved. Bit 0: 1 0 Activates the logical device. Logical device is inactive. CR60, CR61 (Default 0x00, 0x00) These two registers select Pulse Width Modulation base address [0x100:0xFFF] on 8-byte boundary. 9.14 Logical Device C (SMART CARD) CR30 (Default 0x00) Bit [7:1]: Reserved. Bit 0: 1 0 Activates the logical device. Logical device is inactive. CR60, CR61 (Default 0x00, 0x00) These two registers select Smart Card base address [0x100:0xFFF] on 8-byte boundary. CR70 (Default 0x00) Bit [7:4]: Reserved. Bit [3:0]: These bit select IRQ resource for Smart Card interface. CRF0 (Default 0x00) Bit [7:1]: Reserved. Bit 0: 1 0 Smart Card present signal (SCPSNT) is LOW active. SCPSNT is HIGH active. - 117 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 9.15 Logical Device D (URC & GPIO Port 6 ) CR30 (Default 0x00) Bit [7:2]: Reserved. Bit 1: Bit 0: 1 0 1 0 Activate GPIO6. GPIO6 is inactive Activate URC. URC is inactive. CR60, CR61 (Default 0x03, 0xE8 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select the Serial Port 3 I/O base address [0x100:0xFF8] on 8yte boundary. CR62, CR63 (Default 0x00) These two registers select the GPIO6 base address [0x100:0xFFF] on 4byte boundary. IO address: CRF2 base address CR70 (Default 0x00) Bit [7:4]: Reserved. Bit [3:0]: These bits select IRQ resource for Serial Port 3. CRF0 (Default 0x00) Bit 7: Bit 6: Reserved. 1 0 Activates the logical device IRQ sharing function. Logical device IRQ sharing is inactive. Bit [5:2]: Reserved. Bit [1:0]: SUCCLKB1, SUCCLKB0 00 01 10 11 UART C clock source is 1.8462 Mhz (24MHz/13) UART C clock source is 2 Mhz (24MHz/12) UART C clock source is 24 Mhz (24MHz/1) UART C clock source is 14.769 Mhz (24mhz/1.625) CRF1 (GP6 selection register. Default 0xFF) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. Publication Release Date: April 2001 Revision 0.51 - 118 - W83697SF PRELIMINARY CRF2 (GP6 data register. Default 0x00 ) If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF3 (GP6 inversion register. Default 0x00 ) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. CRF4 (GP6 output style register. Default 0x00 ) When set to a '1', the outgoing port is pulse mode. When set to a '0', the outgoing port is level mode. 9.16 Logical Device E (URD & GPIO Port 7 ) CR30 (Default 0x00) Bit [7:2]: Reserved. Bit 1: Bit 0: 1 0 1 0 Activate GPIO7. GPIO7 is inactive Activate URD. URD is inactive CR60, CR61 (Default 0x02, 0xE8 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select the Serial Port 4 I/O base address [0x100:0xFF8] on 8yte boundary. CR62, CR63 (Default 0x00) These two registers select the GPIO7 base address [0x100:0xFFF] on 4byte boundary. IO address : CRF2 base address CR70(Default 0x00) Bit [7:4]: Reserved. Bit [3:0]: These bits select IRQ resource for Serial Port 4. - 119 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY CRF0 (Default 0x00) Bit 7: Bit 6: Reserved. 1 0 Activates the logical device IRQ sharing function. Logical device IRQ sharing is inactive. Bit [5:2]: Reserved. Bit [1:0]: SUDCLKB1, SUDCLKB0 00 01 10 11 UART D clock source is 1.8462 Mhz (24MHz/13) UART D clock source is 2 Mhz (24MHz/12) UART D clock source is 24 Mhz (24MHz/1) UART D clock source is 14.769 Mhz (24mhz/1.625) CRF1 (GP7 selection register. Default 0xFF) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF2 (GP7 data register. Default 0x00 ) If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF3 (GP7 inversion register. Default 0x00 ) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. 9.17 Logical Device F (GPIO Port 8) CR30 (Default 0x00) Bit [7:1]: Reserved. Bit 0: 1 0 Activate GPIO8. PIO8 is inactive. CR60, CR61 (Default 0x00) These two registers select the GPIO8 base address [0x100:0xFFF] on 2byte boundary. IO address : CRF1 base address - 120 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY CRF0 (GP8 selection register. Default 0xFF) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF1 (GP8 data register. Default 0x00 ) If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF2 (GP8 inversion register. Default 0x00 ) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. - 121 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 10.0 ORDERING INSTRUCTION PART NO. W83697SF PACKAGE 128-pin QFP REMARKS 11.0 HOW TO READ THE TOP MARKING Example: The top marking of W83697SF SMART@IO W83697SF 109G5BBBA 1st line: Winbond logo & SMART@IO 2nd line: the type number: W83697SF 3th line: the tracking code 109 G 5B B BA 109: packages made in 2001, week 09 G: assembly house ID; A means ASE, S means SPIL, G means GR, etc. 5B: Winbond internal use. B: IC revision; A means version A, B means version B BA: Winbond internal use. - 122 - Publication Release Date: April 2001 Revision 0.51 W83697SF PRELIMINARY 12.0 PACKAGE DIMENSIONS (128-pin PQFP) HE E 102 65 Symbol Min Dimension in mm Dimension in inch Nom 0.35 2.72 0.20 0.15 14.00 20.00 0.50 Max 0.45 2.87 0.30 0.20 14.10 20.10 Min 0.010 0.101 0.004 0.004 0.547 0.783 Nom Max 0.014 0.107 0.008 0.006 0.551 0.787 0.020 0.018 0.113 0.012 0.008 0.555 0.791 103 64 D HD 128 39 1 e 38 b A1 A2 b c D E e HD HE L L1 y 0 c 0.25 2.57 0.10 0.10 13.90 19.90 17.00 23.00 0.65 17.20 23.20 0.80 1.60 17.40 23.40 0.95 0.669 0.905 0.025 0.677 0.913 0.031 0.063 0.685 0.921 0.037 0.08 0 7 0 0.003 7 Note: 1.Dimension D & E do not include interlead flash. 2.Dimension b does not include dambar protrusion/intrusion . 3.Controlling dimension : Millimeter 4.General appearance spec. should be based on final visual inspection spec. A A2 See Detail F Seating Plane A1 y L L1 Detail F 5. PCB layout please use the "mm". Headquarters No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/ Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064 Winbond Electronics (North America) Corp. 2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their original owners - 123 - Publication Release Date: April 2001 Revision 0.51 |
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